An image sensing device includes a coarse current generation circuit suitable for generating a coarse ramp current adjusted to a coarse level for a single ramp period, a fine current generation circuit suitable for generating a fine ramp current adjusted to a fine level for the single ramp period, and a current-to-voltage conversion circuit suitable for generating a ramp voltage corresponding to a resultant current of the coarse ramp current and the fine ramp current for the single ramp period.

An analog signals generating device comprises a current pump controlled by a control code generated by a module for calculating the digital code with shaping of noise. The calculation module receives as input a digital signal representative of the analog signal to be generated and comprises at least one quantizer and a quantization error compensating stage. The current pump comprises two groups of at least one electric current generator and two groups of at least one switching means, the switching facilities being controlled by the control signal and causing the electric currents to flow between the electric current generators and the inputs of a differential amplifier exhibiting a predominantly capacitive input impedance and connected in series between the two groups of switching means.

The present invention provides an arbitrary waveform generator based on instruction architecture. To deal with the feature that the instructions and waveform data of the AWG are coupled in the prior art, an instruction set based waveform synthesis controller is employed, and substitutes for the sequence wave generator in the present invention, i.e. an arbitrary waveform generator based on instruction architecture. Thus the time-sharing scheduling in reading the waveform synthesis instruction and the segment waveform data is realized, and the complexity of the hardware is reduced, so that the AWG in present invention can synthesize and generate a complex sequence wave rapidly and efficiently.

In accordance with an embodiment, a method includes receiving an enable signal. After the enable signal is asserted, it is determined whether a soft-start capacitor is electrically connected to an input of a ramp generator circuit while keeping an output of the ramp generator circuit low. If the soft-start capacitor is electrically connected to the input of the ramp generator circuit, a first current is injected into the input of the ramp generator circuit to generate a first voltage ramp at the output of the ramp generator circuit. If the soft-start capacitor is not electrically connected to the input of the ramp generator circuit, a second current is injected to the input of the ramp generator circuit to generate a second voltage ramp at the output of the ramp generator circuit. The second current is smaller than the first current.

In accordance with an embodiment, a method includes receiving an enable signal. After the enable signal is asserted, it is determined whether a soft-start capacitor is electrically connected to an input of a ramp generator circuit while keeping an output of the ramp generator circuit low. If the soft-start capacitor is electrically connected to the input of the ramp generator circuit, a first current is injected into the input of the ramp generator circuit to generate a first voltage ramp at the output of the ramp generator circuit. If the soft-start capacitor is not electrically connected to the input of the ramp generator circuit, a second current is injected to the input of the ramp generator circuit to generate a second voltage ramp at the output of the ramp generator circuit. The second current is smaller than the first current.

In accordance with an embodiment, a method includes receiving an enable signal. After the enable signal is asserted, it is determined whether a soft-start capacitor is electrically connected to an input of a ramp generator circuit while keeping an output of the ramp generator circuit low. If the soft-start capacitor is electrically connected to the input of the ramp generator circuit, a first current is injected into the input of the ramp generator circuit to generate a first voltage ramp at the output of the ramp generator circuit. If the soft-start capacitor is not electrically connected to the input of the ramp generator circuit, a second current is injected to the input of the ramp generator circuit to generate a second voltage ramp at the output of the ramp generator circuit. The second current is smaller than the first current.

The present application provides a square wave generating method, applied in a square wave generating circuit, configured to generate a mimetic square wave signal, wherein the square wave generating circuit has a breakdown voltage. The square wave generating method comprises the square wave generating circuit generating the mimetic square wave signal as a first voltage during a first time interval; the square wave generating circuit generating the mimetic square wave signal as a second voltage during a second time interval; and the square wave generating circuit generating the mimetic square wave signal as a transient voltage during a transient interval between the first time interval and the second time interval, wherein the transient voltage is between the first voltage and the second voltage; wherein a first voltage difference between the first voltage and the second voltage is greater than the breakdown voltage.

A spread spectrum clock generator circuit includes a phase comparator; an oscillator to output an output clock signal; a phase selector to select one of phases equally dividing one cycle of the output clock signal, and to generate a phase shift clock signal having a rising edge in the selected phase; and a phase shift controller to control the phase selector. The phase shift controller generates a variable phase shift amount; determines the phase of the rising edge so that the cycle of the phase shift clock signal has a length changed from the cycle of the output clock signal by the variable phase shift amount added with a fixed phase shift amount; and changes a setting of an SS modulation profile if the selected phase exceeds an upper limit, falls below a lower limit, or is within the upper and lower limits.

A spread spectrum clock generator circuit includes a phase comparator; an oscillator to output an output clock signal; a phase selector to select one of phases equally dividing one cycle of the output clock signal, and to generate a phase shift clock signal having a rising edge in the selected phase; and a phase shift controller to control the phase selector. The phase shift controller generates a variable phase shift amount; determines the phase of the rising edge so that the cycle of the phase shift clock signal has a length changed from the cycle of the output clock signal by the variable phase shift amount added with a fixed phase shift amount; and changes a setting of an SS modulation profile if the selected phase exceeds an upper limit, falls below a lower limit, or is within the upper and lower limits.

A voltage level conversion circuit includes a first voltage level input terminal, a second voltage level input terminal, a first thin film transistor, a second thin film transistor, and a delay control chip configured to output the first voltage level before outputting the second voltage level in a delayed manner. The present disclosure also provides a display panel.