According to an embodiment, a semiconductor device includes a comparator and a first circuit. The comparator includes a first input terminal and a second input terminal, and is configured to receive a first voltage at the first input terminal and receive at the second input terminal a second voltage that continuously increases or decreases in a first period. The second voltage is equal in magnitude to the first voltage at a first timing in the first period. The first circuit is configured to change a signal to be output, if a second timing at which an output signal from the comparator is switched is out of a second period including the first timing.

According to an embodiment, a semiconductor device includes a comparator and a first circuit. The comparator includes a first input terminal and a second input terminal, and is configured to receive a first voltage at the first input terminal and receive at the second input terminal a second voltage that continuously increases or decreases in a first period. The second voltage is equal in magnitude to the first voltage at a first timing in the first period. The first circuit is configured to change a signal to be output, if a second timing at which an output signal from the comparator is switched is out of a second period including the first timing.

Aspects of the present disclosure provide for a method. In some examples, the method includes receiving a synchronization signal, dividing the synchronization signal to form a first divided signal and a second divided signal, generating a first ramp signal and a second ramp signal, setting a latch output to a logical high value when the first divided signal has a logical high value or a value of the first ramp signal exceeds a value of a reference signal, setting the latch output to a logical low value when the second divided signal has a logical high value or a value of the second ramp signal exceeds the value of the reference signal, generating a synchronization clock according to the latch output and an inverse of the latch output, and outputting the latch output or the synchronization clock as a clock signal based on a value of a synchronization active signal.

An apparatus for controlling an inverter for driving a motor including a processor which includes: a current processor configured to generate a voltage command for allowing a current detection value, generated by measuring a current provided from an inverter to a motor, to follow a current command for driving the motor; a voltage modulator configured to generate a pulse width modulation signal for controlling on and off states of a switching element within the inverter with a predetermined switching frequency based on the voltage command; and a frequency determining processor configured to randomly change the switching frequency based on driving information of the motor.

A simulation device for simulating a peripheral circuit arrangement that can be connected to a control device, wherein the simulation device can be electrically connected to the control device, and the simulation device has a first control element for influencing a first simulation current that can be passed from a first load terminal of the control device to a first control element output of the first control element. The first control element contains a first multistage converter that includes a first converter output, which is electrically connected to a terminal on the converter side of a first inductive component at whose terminal on the control device side the first control element output is implemented. A direction of flow of the first simulation current is reversible, and the simulation device also includes a computing unit for execution of model code.

A simulation device for simulating a peripheral circuit arrangement that can be connected to a control device, wherein the simulation device can be electrically connected to the control device, and the simulation device has a first control element for influencing a first simulation current that can be passed from a first load terminal of the control device to a first control element output of the first control element. The first control element contains a first multistage converter that includes a first converter output, which is electrically connected to a terminal on the converter side of a first inductive component at whose terminal on the control device side the first control element output is implemented. A direction of flow of the first simulation current is reversible, and the simulation device also includes a computing unit for execution of model code.

A digitally controlled oscillator (100), a synthesizer module (200), a synthesizer (300), and a method for producing an electrical audio signal are presented. The oscillator (100) comprises a digital processing unit (10) configured to generate a first pulse wave at a first output (PulseUp) of the processing unit (10), wherein the first pulse wave is arranged to include pulses at at least two different frequencies. The oscillator (100) further comprises a summing circuit (30) and a linear wave shaper (20). The output (PulseUp) of the processing unit (10) is connected to the summing circuit (30) which is arranged to produce a resultant signal based on at least the first pulse wave. The resultant signal is arranged to be fed into the linear wave shaper (20) which is arranged to produce an output signal at the output (OUT) of the oscillator (100) based on modifying the resultant signal.

A frequency comb generator including a semiconductor, wherein the semiconductor outputs a frequency comb in response to frequency mixing of an optical field and at terahertz field in the semiconductor using a high order sideband (HSG) mechanism. The frequency comb spans a bandwidth sufficient for self-referencing and may be used in optical clock applications, for example.

A frequency comb generator including a semiconductor, wherein the semiconductor outputs a frequency comb in response to frequency mixing of an optical field and at terahertz field in the semiconductor using a high order sideband (HSG) mechanism. The frequency comb spans a bandwidth sufficient for self-referencing and may be used in optical clock applications, for example.

A power continuation control circuit includes a power supply circuit, a detection circuit, an energy storage circuit, a switch module, and a control circuit. The detection circuit is coupled to the power supply circuit. The switch module is coupled to the energy storage circuit. The control circuit is coupled to the switch module and the detection circuit. The power supply output terminal is coupled to the control circuit and the power supply circuit.