An oscillator circuit includes a first integrator unit to charge a first capacitor at a first integration node, a second integrator unit to charge a second capacitor at a second integration node, a chopped comparator unit and a logic unit. The chopped comparator unit includes comprises a switching unit, a sensing comparator and a replica comparator. The switching unit is configured to couple the first integration node, the second integration node and a reference voltage VREF to the sensing comparator and the replica comparator, depending upon a phase determined by a first input clock signal C1 and a second input clock signal C2, which have opposite phases. The logic unit is configured to generate signals C1, C2, D1, D2, E1, E2 for controlling each integrator unit.

Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

Digital-to-analog converter (master DAC) circuitry is disclosed that is programmable to set a controlled slew rate for pulses that are otherwise defined as having sharp amplitude transitions. For example, when producing a biphasic pulse, the constant amplitude and duration of first and second pulses phases can be defined and provided to the DAC in traditional fashion. Slew rate control signals control a slew rate DAC within the master DAC, which prescribes a slew rate that will appear at sharp transitions of the defined biphasic pulses, i.e., at the beginning of the first phase, at the transition from the first to the second phase, and at the end of the second phase. The slew rate can vary with the duration or frequency of the pulses, with lower slew rates used with longer durations and/or lower frequencies, and with higher slew rates used with shorter durations and/or higher frequencies.

Amplification of a signal by a small circuit size and reduction of a power are achieved. A current controlling current source unit 53 changes an outputting current based on a transition time setting signal tp. A current controlling current source unit 54 changes a drawing current based on a transition time setting signal tn. An amplitude control unit 55 changes a power source voltage supplied to the current controlling current source unit 53 and changes amplitude of a voltage generated by a current outputted from the current controlling current source unit 53, based on amplitude setting signal ap. An amplitude control unit 56 changes a power source voltage supplied to the current controlling current source unit 54 and changes amplitude of a voltage generated by the current drawn by the current controlling current source unit 54, based on amplitude setting signal an. The buffer unit 57 drives a load in accordance with the current outputted from the current controlling current source unit 53 and the current drawn from the current controlling current source unit 54.

Amplification of a signal by a small circuit size and reduction of a power are achieved. A current controlling current source unit 53 changes an outputting current based on a transition time setting signal tp. A current controlling current source unit 54 changes a drawing current based on a transition time setting signal tn. An amplitude control unit 55 changes a power source voltage supplied to the current controlling current source unit 53 and changes amplitude of a voltage generated by a current outputted from the current controlling current source unit 53, based on amplitude setting signal ap. An amplitude control unit 56 changes a power source voltage supplied to the current controlling current source unit 54 and changes amplitude of a voltage generated by the current drawn by the current controlling current source unit 54, based on amplitude setting signal an. The buffer unit 57 drives a load in accordance with the current outputted from the current controlling current source unit 53 and the current drawn from the current controlling current source unit 54.

The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less insensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

A capacitive load driving circuit includes a first switching element, a second switching element, a third switching element, a fourth switching element and voltage dropper elements. The first switching element is provided on a first charging path extending from a power supply to a capacitive load. The second switching element is provided on a second charging path extending from a capacitor to the capacitive load. The third switching element is provided on a first discharging path extending from the capacitive load to a ground. The fourth switching element is provided on a second discharging path extending from the capacitive load to the capacitor. The voltage dropper elements are provided on each of control signal power supply paths to the first switching element, to the second switching element, to the third switching element and to the fourth switching element. The voltage dropper elements are configured to make electric current flow more easily through the second charging path than through the first charging path when charging the capacitive load and to make electric current flow more easily through the second discharging path than through the first discharging path when discharging the capacitive load by a potential difference.

A driving circuit includes a comparator that compares a voltage of an original driving signal with a voltage of a feedback signal of a driving signal, transistors, and a control signal generating circuit that generates a gate signal to the transistor and a gate signal to the transistor. The control signal generating circuit controls to alternately switch on the transistors. Driving abilities of the transistors are switched to be lowered by insertion of capacitors by an adjustment circuit.

A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.