A multiphase signal generator includes an input port. Furthermore, the multiphase signal generator includes a plurality of phase shifters. Each phase shifter of the plurality of phase shifters is configured to provide an identical phase shift Δφ. At least one phase shifter is connected to the input port. Furthermore, the multiphase signal generator includes a first phase interpolator and at least a second phase interpolator. Each phase interpolator has a respective output terminal. Each phase interpolator is configured to weight a phase of a signal at a respective first input terminal of the phase interpolator with a respective first weighting factor w.sub.i,1 and to weight a phase of another signal at a respective second input terminal of the phase interpolator with a respective second weighting factor w.sub.i,2 to generate an interpolated phase signal at the respective output terminal of the phase interpolator. A first subset of the plurality of phase shifters includes n>1 serially connected phase shifters. The first subset of phase shifters is coupled between the first input terminal and the second input terminal of the first phase interpolator. A different second subset of the plurality of phase shifters includes n serially connected phase shifters. The second subset of phase shifters is coupled between the first input terminal and the second input terminal of the second phase interpolator.

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values. The control signal generator is configured to generate a control signal based on an input clock signal and values in the at least a portion of the registers, wherein the control generator sequentially generates the control signal during each cycle of the input clock signal. The clock gating circuit is configured to refer to the control signal to mask or not mask the input clock signal to generate an output clock signal.

A transceiver circuit is configured to couple an oscillation crystal. The transceiver circuit includes a local oscillator, a filter circuit, a control circuit, and a radio frequency signal generator circuit. The local oscillator includes a capacitive element. The local oscillator generates a phase locked loop signal based on an oscillation frequency of the oscillation crystal and a capacitance value of the capacitive element. The filter circuit generates a filtered signal according to the phase locked loop signal. The control circuit adjusts the capacitance value to be an adjusted capacitance value according to the filtered signal and the phase locked loop signal. The local oscillator further generates a calibrated local oscillation signal according to the oscillation frequency and the adjusted capacitance value. The radio frequency signal generator circuit generates a radio frequency signal according to the calibrated local oscillation signal and a baseband signal.

An AND gate comprises: a first input; a second input; an output; and a plurality of field effect transistors, FETs, each having a respective first terminal, a respective second terminal, and a respective gate terminal to which a voltage may be applied to control a conductivity of a respective channel between the respective first terminal and the respective second terminal. The plurality of FETs comprises: a first FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the second input; a second FET having its first terminal directly connected to the first input, its second terminal directly connected to the output, and its gate terminal directly connected to the output; and a third FET having its first terminal directly connected to the second input, its second terminal directly connected to the output, and its gate terminal directly connected to the output. Also disclosed is a clock divider stage for receiving a first clock signal oscillating at a first frequency and a second clock signal, the second clock signal being an inversion of the first clock signal, and generating a first output clock signal oscillating at half of the first frequency.

In accordance with an embodiment, a method includes: receiving, by an adjustable frequency doubling circuit, a first clock signal having a first clock frequency; using the adjustable frequency doubling circuit, generating a second clock signal having a second clock frequency that is twice the first clock frequency; measuring a duty cycle parameter of the second clock signal, where the duty cycle parameter is dependent on a duty cycle of the first clock signal or a duty cycle of the second clock signal; and using the adjustable frequency doubling circuit, adjusting the duty cycle of the first clock signal or the second clock signal based on the measuring.

It is described a signal converter device (100) for converting a single-ended signal to a differential signal, the device (100) comprising: i) a multiplier device (110), configured to receive a single-ended incoming signal (105), and multiply the incoming signal (105) to provide a multiplied signal (115); and ii) a divider device (120), configured to receive the multiplied signal (115), and divide the multiplied signal (115) to provide a differential signal (125a, 125b).

Further, a corresponding signal conversion method is described.

In order to suppress frequency fluctuation caused by a load frequency, an AR calculating section calculates an AR using system frequency deviation and tie-line power flow deviation as inputs. An output distribution ratio determining section determines a ratio of output distribution according to merit order based on the AR calculated by the AR calculating section. An output distributing section determines output distribution according to an output change speed based on the output distribution ratio determined by the output distribution ratio determining section according to the output change speed. An output distributing section determines output distribution according to the merit order based on the output distribution ratio determined by the output distribution ratio determining section according to the merit order. An output distribution instruction value determining section determines an output distribution instruction value to each regulated power source using, as inputs, output distribution values determined by the output distributing sections.

A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.

Disclosed is a frequency multiplication apparatus including a first frequency multiplier receiving a first signal having a first frequency and outputting a second signal having a second frequency by multiplying the first frequency by ‘n’ (‘n’ being a positive integer), a second frequency multiplier receiving the second signal and outputting a third signal having a third frequency by multiplying the second frequency by ‘m’ (‘m’ being a positive integer), and a coupler connected between an output of the first frequency multiplier and an input of the second frequency multiplier and outputting a part of the second signal.

Described herein are nodes, sub-systems and systems of nodes for use in a dynamic node based computer. In some embodiments, nodes include: one or more signal receivers for detecting or receiving one or more input signals from one or more signal sources, one or more signal transmitters for selectively connecting and transmitting signals to one or more other nodes; and a threshold device configured to control the selective operation of the signal transmitter based on a threshold derived from one or more characteristics of the input signals. More complex variations of the nodes include the addition of threshold manipulation devices, signal amplifiers or dampeners, control devices, or computational devices. Also described herein are machines or devices built from one or more such nodes.