A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners.

An apparatus for generating a plurality of phase-shifted clock signals is provided. The apparatus comprises a first input node configured to receive a first reference clock signal. Further, the apparatus comprises a second input node configured to receive a second reference clock signal. The apparatus comprises a plurality of output nodes each configured to output one of the plurality of phase-shifted clock signals. Additionally, the apparatus comprises a cascade of coupled clock generation circuits configured to generate the plurality of phase-shifted clock signals based on the first reference clock signal and the second reference clock signal. Input nodes of the first clock generation circuit of the cascade of clock generation circuits are coupled to the first input node and the second input node. Output nodes of the last clock generation circuit of the cascade of clock generation circuits are coupled to the plurality of output nodes. At least one of the plurality of clock generation circuits is an active circuit, and at least one of the plurality of clock generation circuits is a passive circuit.

A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.

There is provided a phase shifter circuit of an optical encoder that receives four signals generated from photodiodes. The phase shifter circuit includes four resistor strings each coupled to two of the four signals having a 90-degrees phase pitch. By taping out different numbers of signals at different tape-out nodes of each of the four resistor strings, the phase shifter circuit is adapted to output signals for different interpolation factors without changing the mask set.

A device for controlling transmission of electromagnetic waves according to the present disclosure includes: a conductor line which is positioned on a signal layer and through which electromagnetic waves received via an input terminal travel; a ground layer electrically separated from the signal layer through a dielectric layer and electrically grounded; a shunt via including a first end and a second end and connected to the conductor line through the first end; and a photoconductive semiconductor connected between the second end of the shunt via and the ground layer and having a dielectric state or a conducting state, based on an input of an optical signal, wherein the conductor line is electrically connected to the ground layer via the shunt via and the photoconductive semiconductor in the conducting state, thereby causing reflection of electromagnetic waves from the shunt via.

Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

A digital clock circuit is provided. The digital clock circuit includes a first sub-circuit comprising a first digitally-controlled oscillator driven by a frequency control word to control a first output frequency synthesized from multiple first pulses, and a first frequency divider to generate a trigger signal having a frequency equal to 1/M of the first output frequency. The digital clock circuit also includes a second sub-circuit comprising a loop of feedback including a frequency detector to compare an input frequency with a feedback frequency, a controller to adjust the frequency control word, a second digitally-controlled oscillator driven by the frequency control word plus a constant to control a second output frequency synthesized from multiple second pulses induced by the trigger signal, and a second frequency divider to set the feedback frequency equal to 1/N of the second output frequency in the loop of feedback.

A data receiving circuit may include: a variable delay circuit suitable for generating a delayed strobe signal by delaying a strobe signal; a receiving circuit suitable for sampling data in synchronization with the delayed strobe signal; a phase shift circuit suitable for generating a shifted strobe signal by shifting a phase of the delayed strobe signal; a phase comparison circuit suitable for comparing phases of the data and the shifted strobe signal; and a delay adjusting circuit suitable for adjusting a delay value of the variable delay circuit in response to the phase comparison result of the phase comparison circuit.

A method for in-phase (I) and quadrature (Q) signal generation is disclosed. The method may include a first stage receiving a differential input signal. The first stage may also generate first differential in-phase and quadrature output signals, which may be sent by the first stage to a second stage. The second stage may generate second differential in-phase and quadrature output signals, which may have amplitude and phase mismatches less than an amplitude and phase mismatches of the first differential output signals. The second stage may then output the second differential I/Q output signals.