A semiconductor package includes a first die having a phase locked loop outputting a local clock signal and a strobe signal to a first transmit block of the first die. The strobe signal has a phase offset relative to the local clock signal. A second die is aligned with the first die so each of a first plurality of connection points of the first die is substantially equidistant to a corresponding connection point of a second plurality of connection points of the second die. A plurality of connection paths of a substantially same length couple a connection points of the first plurality of connection points to corresponding connection points of the second plurality of connection points. Different connection paths transmit data signals from the first die to the second die based on the local clock signal and transmit the strobe signal from the first die to the second die.

Systems and methods disclosed herein include a correction circuit. The correction circuit may include frequency division circuitry that is configured to receive and condition a reference signal. The correction circuit may include drive circuitry that is configured to receive the reference signal. The correction circuit may include a first resonator that is configured to receive the reference signal. The correction circuit may include sense circuitry that is configured to receive the reference signal from the first resonator. The correction circuit may include phase detector circuitry that is configured to generate at least one output signal based on receipt of a plurality of input signals from the drive circuitry and the sense circuitry. The correction circuit may include a proportional integral derivative controller that is configured to generate a temperature correction signal to correct frequency error in an oscillator based on receipt of the at least one output signal.

A phase adjusting device provided includes a main delay circuit, a first converter, a second converter, a first buck circuit, and a second buck circuit. The main delay circuit receives an input clock signal to generate a main delay signal. The first converter receives the input clock signal to generate a first conversion signal. The second converter is coupled to the main delay circuit to receive the main delay signal and generate a second conversion signal. The first buck circuit is coupled to the first converter to receive the first conversion signal and generate a first buck voltage. The second buck circuit is coupled to the second converter to receive the second conversion signal and generate a second buck voltage. A first phase difference is formed between the main delay signal and the input clock signal.

In embodiments of the present disclosure, weighting on a direct current component coefficient dc.sub.i of an I-channel signal and a direct current component coefficient dc.sub.q of a Q-channel signal is performed based on spatial leakage factors k1 and k2 of a microwave chip and a current attenuation amount of a tunable attenuator, to determine a corrected direct current component coefficient dc.sub.i of the I-channel signal and a corrected direct current component coefficient dc.sub.q of the Q-channel signal, and a direct current component superimposed to the I-channel signal of the microwave chip and a direct current component superimposed to the Q-channel signal of the microwave chip are respectively determined based on the corrected direct current component coefficient dc.sub.i of the I-channel signal and the corrected direct current component coefficient dc.sub.q of the Q-channel signal.

Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

An analog-based architecture is used to produce tap spacings in an n-tap fractionally-spaced equalizer without the need for digital clock-driven elements. The analog voltage-controlled delay cell circuits control the amount of applied delay based on the measured phase difference between quarter-rate clock signals. Because low speed clock signals are sufficient for comparison purposes, the analog delay cells can be placed before the quarter-rate multiplexors in the data path. The use of analog-based delay cells eliminates the need to route high-speed clock signals to multiple digital delay elements that are typically used to achieve fractionally spaced data signals in n-tap FIR equalizers. Timing margin issues can also be eliminated since digital clocked elements are not used to produce the fractionally spaced delays. The analog-based delay approach also consumes less power relative equalizers that use multiple digital delay elements requiring high speed clock signals.

A processing device identifies clock phases of a multiphase clock system. The processing device selects a first clock phase and a second clock phase of the clock phases. The processing device determines an aggregate phase distance between the first clock phase and the second clock phase over multiple clock periods. The processing device determines, based on the aggregate phase distance, an aggregate time duration between the first clock phase and the second clock phase over the multiple clock periods of the multiphase clock system.

A method, a phase shifter, and a user equipment (UE) are disclosed for transmitting and receiving signals in a phased array. The method includes receiving, by a balun of a phase shifter, a transmission single-ended input signal at a single-ended side of the balun and generating a transmission differential input signal at a differential side of the balun, generating, by a differential quadrature coupler of the phase shifter, a transmission in-phase signal and a transmission quadrature signal, based on the transmission differential input signal, and combining, by a differential attenuator of the phase shifter, the transmission in-phase signal and the transmission quadrature signal into a differential phase-shifted output signal.

A metamaterial comprises a plurality of electrically controllable metamaterial units each comprising a varactor diode; the predetermined angle is an angle at which an electromagnetic wave is reflected from a surface of the metamaterial; there is an association relationship between the predetermined angle and the first phase difference; the method comprises: determining a first phase difference between electromagnetic waves reflected by two adjacent electrically controllable metamaterial units in a metamaterial based on a predetermined angle; determining a target capacitance of the varactor diode in each electrically controllable metamaterial unit based on the first phase difference; and adjusting a capacitance of the varactor diode in each electrically controllable metamaterial unit to the target capacitance.