A phase coherent synthesizer with good phase noise and spurious performance is described. The phase coherent synthesizer includes digital direct synthesizer (DDS) circuitry, frequency multiplier circuitry, an oscillator, and a mixing stage. The digital direct synthesizer (DDS) circuitry has a first output and a second output. The first output is associated with a fine resolution synthesis. The second output is associated with a step synthesis. A second output signal provided via the second output has a higher frequency compared with a first output signal provided via the first output. The frequency multiplier circuitry is connected with the second output. The frequency multiplier circuitry is configured to multiply the second output signal received via the second output, thereby generating a multiplied output signal. The mixing stage has two input ports connected with the frequency multiplier circuitry and the oscillator respectively. The mixing stage includes, for example, circuitry configured to mix the multiplied output signal and an oscillator output signal of the oscillator, thereby generating an intermediate frequency signal. The first output signal and the intermediate frequency signal are synchronized with each other.

An RF phase offset detection system, which includes a first RF phase detector and a second RF phase detector, and measures a first phase offset between a first RF signal and a second RF signal, is disclosed. Each of the first RF signal and the second RF signal has a common RF frequency. The first RF phase detector detects and filters the first RF signal and the second RF signal to provide a first detection signal. The second RF phase detector receives and phase-shifts the second RF signal to provide a phase-shifted RF signal. The second RF phase detector further detects and filters the first RF signal and the phase-shifted RF signal to provide a second detection signal, such that a combination of the first detection signal and the second detection signal is representative of the first phase offset.

Embodiments of the present invention provide for anion exchange membranes and processes for their manufacture. The anion exchange membranes described herein are made the polymerization product of at least one functional monomer comprising a tertiary amine which is reacted with a quaternizing agent in the polymerization process.

An integrated circuit includes a first input port configured to receive a supply voltage from a switched-mode power supply (SMPS), where frequency components of the supply voltage include harmonics of a reference frequency, where the reference frequency is equal to a first frequency divided by a factor; and a spurious components cancellation circuit coupled to the first input port, where the spurious components cancellation circuit is configured to: generate a first clock signal having the reference frequency; adjust an amplitude and a phase of the first clock signal to form a compensation signal; and add the compensation signal to the supply voltage to produce a modified supply voltage with reduced frequency components at one or more harmonic frequencies of the reference frequency.

A phase-shifted sampling module for sampling a signal is described. The phase-shifted sampling module includes a primary sampler module, an ADC module, and an equalization module. The primary sampler module includes an analog signal input, a first signal path, and a second signal path. The equalization module includes a primary sampler equalizer sub-module. The primary sampler equalizer sub-module is configured to compensate low-frequency mismatches between the first signal path and the second signal path. Further, a method for determining filter coefficients of an equalization module of a phase-shifted sampling module is described.

Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.

Embodiments described herein provide a method of separating a liquid mixture, comprising providing a liquid mixture to a separator, electrically coupling a power circuit to the liquid mixture inside the separator, applying a time-varying voltage to the power circuit, detecting a phase angle in the power circuit; and controlling the phase angle by adjusting a characteristic of the time-varying voltage.

An electronic circuit and method are provided. The electronic circuit includes an in-phase(I)-quadrature(Q) amplifier including an I cascode branch and a Q cascode branch, the IQ amplifier configured to receive a differential input and control signals, control, based on the control signals, gate voltages in the I cascode branch and gate voltages in the Q cascode branch, generate an I output signal with the I cascode branch, and generate a Q output signal with the Q cascode branch, and a quadrature coupler configured to perform quadrature summation of the I output signal and the Q output signal and generate a final phase shifted output.

There is provided an interpolation circuit of an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals sequentially have a 90 degrees phase shift and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

An apparatus which includes a multiphase signal generator circuit. The multiphase signal generator circuit is configured to receive as input a complementary analog signal having a fundamental frequency, and generate a plurality of output complementary analog signals. Each output complementary analog signal comprises the same fundamental frequency as the input complementary analog signal, and wherein each output complementary analog signal comprises a different phase.