Patent classifications
H03K2005/00286
PHASE DEMODULATOR WITH NEGATIVE FEEDBACK LOOP
Disclosed is a phase demodulator, which includes a transmitter that outputs a reference signal to a target, a receiver that receives a target signal generated in response to the reference signal from the target, and a demodulation processor that demodulates the target signal, and the demodulation processor includes a phase controller that outputs a first phase signal based on the reference signal, a phase shifter that delays a phase of the first phase signal to output a first delayed signal, a mixer that outputs a first mixing signal based on the target signal and the first delay signal, and an amplifier that outputs a first feedback signal generated by amplifying the first mixing signal to the phase controller.
Precision High Frequency Phase Adders
An electronic circuit including: a differential multiplier circuit with a first differential input and a second differential input and a differential output; and a phase locked loop (PLL) circuit including: (1) a balanced differential mixer circuit with a first differential input electrically connected to the differential output of the differential multiplier circuit, a second differential input, and an output; (2) a loop filter having an output and an input electrically connected to the output of the balanced differential mixer circuit; and (3) a voltage controlled oscillator (VCO) circuit having an input electrically connected to the output of the loop filter and with an output electrically feeding back to the second differential input of the balanced differential mixer circuit.
Method for controlling transmission of electromagnetic wave on basis of light, and device therefor
A device for controlling transmission of electromagnetic waves according to the present disclosure includes: a conductor line which is positioned on a signal layer and through which electromagnetic waves received via an input terminal travel; a ground layer electrically separated from the signal layer through a dielectric layer and electrically grounded; a shunt via including a first end and a second end and connected to the conductor line through the first end; and a photoconductive semiconductor connected between the second end of the shunt via and the ground layer and having a dielectric state or a conducting state, based on an input of an optical signal, wherein the conductor line is electrically connected to the ground layer via the shunt via and the photoconductive semiconductor in the conducting state, thereby causing reflection of electromagnetic waves from the shunt via.
METHOD AND CIRCUIT FOR POWER CONSUMPTION REDUCTION IN ACTIVE PHASE SHIFTERS
An electronic circuit and method are provided. The electronic circuit includes an amplifier including first cascode branch and a second cascode branch, the amplifier being configured to receive a differential input and control signals, control gate voltages in the first cascode branch and gate voltages in the second cascode branch, generate a first output signal with the first cascode branch, and generate a second output signal with the second cascode branch, and a coupler configured to perform a summation of the first output signal and the second output signal, and generate a final phase shifted output, wherein the first cascode branch or the second cascode branch includes a first cascode arm and a second cascode arm.
Semiconductor device
A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.
Phase demodulator with negative feedback loop
Disclosed is a phase demodulator, which includes a transmitter that outputs a reference signal to a target, a receiver that receives a target signal generated in response to the reference signal from the target, and a demodulation processor that demodulates the target signal, and the demodulation processor includes a phase controller that outputs a first phase signal based on the reference signal, a phase shifter that delays a phase of the first phase signal to output a first delayed signal, a mixer that outputs a first mixing signal based on the target signal and the first delay signal, and an amplifier that outputs a first feedback signal generated by amplifying the first mixing signal to the phase controller.
LOW-LOSS BI-DIRECTIONAL PASSIVE LSB PHASE SHIFTER IN MM-WAVE CMOS
A phase shifter with a first port and a second port has a triple inductor network with a center inductor connected to the first port and the second port, and first and second peripheral inductors each electromagnetically coupled to the center inductor. A resistance switch network that is connected to the first and second peripheral inductors. The resistance switch network is selectively activatable to set a first state defined at least by a first resistance in a series circuit with the first and second peripheral inductors, a second state defined at least by a second resistance in the series circuit, and a third state defined at least by a third resistance in the series circuit. A transmission signal from the first port to the second port is shifted in phase by a prescribed angle corresponding to forward transmission coefficients for the first state, second state, and third state.
Waveform generation circuit for finely tunable sensing frequency
Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.
Calibrating a phase interpolator by amplifying timing differences
Systems and methods related to calibrating a phase interpolator by amplifying timing differences are described. An example system includes a calibration stage configured to output a calibration code for a phase interpolator. The system further includes control logic configured to: (1) at least partially discharge a first pre-charged capacitive load in response to a signal output by the phase interpolator based on the calibration code, and (2) at least partially discharge a second pre-charged capacitive load in response to a reference signal associated with the phase interpolator. The system further includes a feedback path configured to provide feedback to the calibration stage to allow for a modification of the calibration code, where the feedback is dependent on a first voltage provided by the first pre-charged capacitive load and a second voltage provided by the second pre-charged capacitive load.
MILLIMETER WAVE TRANSMITTER
A millimeter wave (MMW) circuitry includes a phase modulation circuitry, a plurality of amplifier multiplier chain circuitries and a power combiner circuitry. The phase modulation circuitry is configured to receive input data and a plurality of divided input signals and to provide as output a plurality of phase modulation circuitry output signals. Each phase modulation circuitry output signal corresponds to a respective divided input signal. At least one phase modulation circuitry output signal has a nonzero phase relative to the divided input signals that is related to the input data. Each amplifier multiplier chain circuitry is configured to amplify and frequency multiply and phase multiply the respective phase modulation circuitry output signal to yield a respective power combiner input signal. The power combiner circuitry is configured to sum a plurality of power combiner input signals to yield an output signal. A modulation of the output signal is related to the input data.