A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.

A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

A level converter for a vehicle control device, including: a first voltage terminal; a second voltage terminal; at least one output terminal; an input terminal; a first switch for switching a first current path between the first voltage terminal and the at least one output terminal or one of the output terminals; and a second switch for switching a second current path between the second voltage terminal and the at least one output terminal or another of the output terminals; the first and second switches being switchable in response to different levels at the input terminal so that when a first level is present at the input terminal, the first switch is closed and the second switch is open, and so that when a second level is present, the first switch is open and the second switch is closed. Also described is a related control device, utility vehicle and method.

A level converter for a vehicle control device, including: a first voltage terminal; a second voltage terminal; at least one output terminal; an input terminal; a first switch for switching a first current path between the first voltage terminal and the at least one output terminal or one of the output terminals; and a second switch for switching a second current path between the second voltage terminal and the at least one output terminal or another of the output terminals; the first and second switches being switchable in response to different levels at the input terminal so that when a first level is present at the input terminal, the first switch is closed and the second switch is open, and so that when a second level is present, the first switch is open and the second switch is closed. Also described is a related control device, utility vehicle and method.

A common mode voltage level shifting and locking circuit is provided. The common mode voltage level shifting and locking circuit includes an operational amplifier, a source follower, a first feedback circuit, and a second feedback circuit. The operational amplifier generates a first common mode voltage. The source follower shifts the first common mode voltage to generate a second common mode voltage. The first feedback circuit generates a first control signal according to the second common mode voltage. The operational amplifier adjusts the first common mode voltage according to the first control signal. The second feedback circuit generates a second control signal according to an external reference voltage provided by a next stage circuit. The source follower adjusts the second common mode voltage according to the second control signal such that the next stage circuit reaches a maximum input common mode range.

A switch mode power supply includes an error amplifier, an oscillator, a pulse width modulation logic circuit, and an output stage. The oscillator includes a current generator that receives a clock signal and provides a current proportional to a frequency of the clock signal, a current mirror having an input coupled to the output of the current generator, and a first capacitor having a first terminal coupled to an output of the current mirror and providing a ramp signal, and a second terminal coupled to power supply voltage terminal. The pulse width modulation logic circuit compares the output of the error amplifier with the ramp signal, and generates a high- and low-side drive signals respectively to first and second outputs in response to the comparing. The output stage is responsive to the high- and low-side drive signals for alternatively coupling a switch terminal between an input voltage terminal and ground.

A switch mode power supply includes an error amplifier, an oscillator, a pulse width modulation logic circuit, and an output stage. The oscillator includes a current generator that receives a clock signal and provides a current proportional to a frequency of the clock signal, a current mirror having an input coupled to the output of the current generator, and a first capacitor having a first terminal coupled to an output of the current mirror and providing a ramp signal, and a second terminal coupled to power supply voltage terminal. The pulse width modulation logic circuit compares the output of the error amplifier with the ramp signal, and generates a high- and low-side drive signals respectively to first and second outputs in response to the comparing. The output stage is responsive to the high- and low-side drive signals for alternatively coupling a switch terminal between an input voltage terminal and ground.

A common signal attenuation circuit may include a sensing block suitable for sensing differential signals to generate sensed differential signals; a common signal generation block suitable for generating an common signal having a common voltage noise by combining the sensed differential signals; and an attenuation block suitable for adjusting the common voltage noise in the original common signal by combining the common signal having the adjusted common voltage noise to the differential signals.

A common signal attenuation circuit may include a sensing block suitable for sensing differential signals to generate sensed differential signals; a common signal generation block suitable for generating an common signal having a common voltage noise by combining the sensed differential signals; and an attenuation block suitable for adjusting the common voltage noise in the original common signal by combining the common signal having the adjusted common voltage noise to the differential signals.