A level converter for a vehicle control device, including: a first voltage terminal; a second voltage terminal; at least one output terminal; an input terminal; a first switch for switching a first current path between the first voltage terminal and the at least one output terminal or one of the output terminals; and a second switch for switching a second current path between the second voltage terminal and the at least one output terminal or another of the output terminals; the first and second switches being switchable in response to different levels at the input terminal so that when a first level is present at the input terminal, the first switch is closed and the second switch is open, and so that when a second level is present, the first switch is open and the second switch is closed. Also described is a related control device, utility vehicle and method.

Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.

Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.

Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

A method of processing a liquid by an alternating electromagnetic field includes: generating DC pulses by a pulse generator; and applying the DC pulses to a parallel oscillating circuit connected in parallel to the pulse generator. The parallel oscillating circuit includes an inductor connected in parallel to a capacitor. In response to the DC pulses, self-oscillations arise in the parallel oscillating circuit, the self-oscillations producing an alternating current in the inductor; and the inductor generates the alternating electromagnetic field for processing the liquid.

A method of processing a liquid by an alternating electromagnetic field includes: generating DC pulses by a pulse generator; and applying the DC pulses to a parallel oscillating circuit connected in parallel to the pulse generator. The parallel oscillating circuit includes an inductor connected in parallel to a capacitor. In response to the DC pulses, self-oscillations arise in the parallel oscillating circuit, the self-oscillations producing an alternating current in the inductor; and the inductor generates the alternating electromagnetic field for processing the liquid.

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion (e.g. DC/DC) and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. According to an aspect, timing control of edges of a control signal to the high voltage semiconductor devices is provided by a basic edge delay circuit that includes a transistor, a current source and a capacitor. An inverter can be selectively coupled, via a switch, to an input and/or an output of the basic edge delay circuit to allow for timing control of a rising edge or a falling edge of the control signal.

Methods and devices for generating a voltage waveform at an output may include providing four DC voltages of different magnitudes. The first (V.sub.1) magnitude is higher than the third (V.sub.3) and fourth (V.sub.4) magnitude. The fourth DC voltage is coupled to the output followed by coupling the first DC voltage to the output, to bring an output voltage (V.sub.P) at the output to a high level. The first DC voltage is decoupled from the output, followed by coupling the third DC voltage to the output, to obtain a drop of the output voltage (V.sub.P). A ground potential (V.sub.0) is coupled to the output following coupling the third DC voltage and the second DC current (I.sub.2) is coupled to the output following coupling the ground potential, wherein the second DC current ramps down the output voltage (V.sub.P).