The application provides a dispersed carrier phase-shifting method and system. The method includes connecting at least two power modules to form a modular system; each power module including a control module for sampling at least twice a common state variate, signs of slopes of the common state variate at a first and second sampling time are opposite, and a reference time of the first sampling time for each control module is the same; and regulating a carrier frequency of the power module according to a relative size between a sampled values at the first and second sampling time. According to embodiments herein, carrier phase-shifting of modular system may be implemented without communication between respective modules. Under closed-loop control, optimal carrier phase-shifting can be automatically achieved under various duty ratios, thereby having good stability.

A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.

A system includes a mixer of a phase interpolator. The mixer includes a dynamic load whose output signal is coupled to a subsequent stage of the phase interpolator. The dynamic load is configured to provide an alternating current (AC) signal to the subsequent stage of the phase interpolator as input clock signals. The mixer further includes a static load whose output signal is coupled to the subsequent stage of the phase interpolator in parallel with the respective output signal line of the dynamic load. The static load configured to provide a direct current (DC) signal to the phase interpolator temporarily in replacement of the respective AC signals to prevent output signals of the subsequent stage of the phase interpolator from being unpredictable.

A strong and weak hybrid PUF circuit comprises N switch units and an arbiter. Each switch unit consists of two delay modules and two 2:1 multiplexers. The N switch units constitute two completely symmetrical delay paths. Each delay module consists of six stages of delay cells. During the operating process, a transmission signal selects a turn-on path of the corresponding 2:1 multiplexers according to activation signals; the switch units in the PUF circuit are in a valid state (if the delay modules are turned on) or in an invalid state (if the delay modules are not turned on) according to whether the delay modules are turned during the operating process; and the strong and weak hybrid PUF circuit can be flexibly configured to be of two different types (a strong PUF circuit and a weak PUF circuit) according to changes of the Hamming weight of input activation signals.

A strong and weak hybrid PUF circuit comprises N switch units and an arbiter. Each switch unit consists of two delay modules and two 2:1 multiplexers. The N switch units constitute two completely symmetrical delay paths. Each delay module consists of six stages of delay cells. During the operating process, a transmission signal selects a turn-on path of the corresponding 2:1 multiplexers according to activation signals; the switch units in the PUF circuit are in a valid state (if the delay modules are turned on) or in an invalid state (if the delay modules are not turned on) according to whether the delay modules are turned during the operating process; and the strong and weak hybrid PUF circuit can be flexibly configured to be of two different types (a strong PUF circuit and a weak PUF circuit) according to changes of the Hamming weight of input activation signals.

A voltage generation circuit includes a plurality of rectification circuits configured to be selectively activated depending on a plurality of first control signals, and to generate an internal voltage according to respective reference voltages capable of being independently trimmed depending on a plurality of second control signals; a detection circuit configured to generate a detection signal by comparing a pre-detection signal, generated in each of the plurality of rectification circuits, and a reference signal; and a storage circuit configured to store a pre-select signal provided from an external system, and to output a stored signal to each of the plurality of rectification circuits as the plurality of second control signals.

A voltage generation circuit includes a plurality of rectification circuits configured to be selectively activated depending on a plurality of first control signals, and to generate an internal voltage according to respective reference voltages capable of being independently trimmed depending on a plurality of second control signals; a detection circuit configured to generate a detection signal by comparing a pre-detection signal, generated in each of the plurality of rectification circuits, and a reference signal; and a storage circuit configured to store a pre-select signal provided from an external system, and to output a stored signal to each of the plurality of rectification circuits as the plurality of second control signals.

An electrical system is provided. The electrical system comprises a first phase lock circuit embedded within a first chip for receiving a first periodic signal having a first frequency. The electrical system comprises a first buffering circuit embedded within the first chip for receiving a second periodic signal having the first frequency, wherein the first buffering circuit is configured to provide a third periodic signal having the first frequency to an output terminal of the first chip.