The present disclosure relates to a pre-5.sup.th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4.sup.th-Generation (4G) communication system such as Long Term Evolution (LTE). An apparatus of a terminal in a wireless communication system is provided. The apparatus includes at least one transceiver and at least one processor operatively coupled to the at least one transceiver. The at least one processor is configured to control the transceiver to communicate through a cell determined based on information regarding a strength of a received signal for a first cell and a path diversity (PD) for the first cell. The PD comprises information regarding paths associated with the first cell.

A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.

A latency controller within an integrated circuit device retimes command-stream-triggered control and timing signals into endpoint timing domains having respective time-varying phase offsets relative to a reference clock by iteratively estimating and logging the phase offsets independently of commands streaming into the integrated circuit device.

The present disclosure relates to the field of analog integrated circuit technology. A digital and analog mixed signal control circuit for eliminating a degenerate metastable state of a self-biased bandgap reference circuit utilizes a digital-to-analog converter module with low-power consumption and flexibly customized accuracy as needed, a delay switch, and a non-volatile memory cell to directly control and clamp a circuit node at the degenerate metastable state in the bandgap reference circuit module, and to release the clamping after a certain delay. Such control mechanism effectively prevents the self-biased bandgap reference circuit with an operational amplifier from entering the degenerate metastable state, and enhance robustness of the circuit, such that the reference circuit is capable of starting normally under various conditions, which improves the performance and yield of the products.

The present disclosure relates to the field of analog integrated circuit technology. A digital and analog mixed signal control circuit for eliminating a degenerate metastable state of a self-biased bandgap reference circuit utilizes a digital-to-analog converter module with low-power consumption and flexibly customized accuracy as needed, a delay switch, and a non-volatile memory cell to directly control and clamp a circuit node at the degenerate metastable state in the bandgap reference circuit module, and to release the clamping after a certain delay. Such control mechanism effectively prevents the self-biased bandgap reference circuit with an operational amplifier from entering the degenerate metastable state, and enhance robustness of the circuit, such that the reference circuit is capable of starting normally under various conditions, which improves the performance and yield of the products.

Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

Apparatuses and methods to reduce leakage current are presented. The includes a switch circuit configured to power a circuit block; a delay circuit configured to delay enabling the switch circuit powering the circuit block and to be powered down; and a bypass circuit configured to bypass the delay circuit to disable the switch circuit powering the circuit block. The method includes powering, by switch, a circuit block; powering down a delay circuit; and bypassing, by a bypass circuit, the delay circuit to disable the switch circuit powering the circuit block.

This application discloses an alternating-current energy detection apparatus, in which a voltage detection unit forms a coupling capacitance together with a tested cable, obtains a first voltage based on an actual voltage and the coupling capacitance, and outputs the first voltage to a data processing unit; a current detection unit detects a tested-cable current, and outputs the tested-cable current to the data processing unit; and the data processing unit receives the first voltage and the tested-cable current, and determines a first voltage value and a tested-cable current value; calculates a product of the first voltage value and a quantity of amplification times of a tested-cable voltage, and determines a tested-cable voltage value; and calculates, based on the tested-cable voltage value and the tested-cable current value, electric energy transmitted by the tested cable.

This application discloses an alternating-current energy detection apparatus, in which a voltage detection unit forms a coupling capacitance together with a tested cable, obtains a first voltage based on an actual voltage and the coupling capacitance, and outputs the first voltage to a data processing unit; a current detection unit detects a tested-cable current, and outputs the tested-cable current to the data processing unit; and the data processing unit receives the first voltage and the tested-cable current, and determines a first voltage value and a tested-cable current value; calculates a product of the first voltage value and a quantity of amplification times of a tested-cable voltage, and determines a tested-cable voltage value; and calculates, based on the tested-cable voltage value and the tested-cable current value, electric energy transmitted by the tested cable.

A pulse shaping device includes an inductor that is selectively output-coupled to a first port of a capacitor. The inductor is charged to a selected current throughput and then coupled to the first port to generate a first characteristic within the current flowing at a second port of the capacitor. The capacitor is charged until reaching a clamping voltage at the first port. A voltage clamp of the shaping device clamps the first port of the capacitor at the clamping voltage to generate a second characteristic within the current flowing at a second port of the capacitor.