A pulse shaping device includes an inductor that is selectively output-coupled to a first port of a capacitor. The inductor is charged to a selected current throughput and then coupled to the first port to generate a first characteristic within the current flowing at a second port of the capacitor. The capacitor is charged until reaching a clamping voltage at the first port. A voltage clamp of the shaping device clamps the first port of the capacitor at the clamping voltage to generate a second characteristic within the current flowing at a second port of the capacitor.

A voltage generation circuit includes a plurality of rectification circuits configured to be selectively activated depending on a plurality of first control signals, and to generate an internal voltage according to respective reference voltages capable of being independently trimmed depending on a plurality of second control signals; a detection circuit configured to generate a detection signal by comparing a pre-detection signal, generated in each of the plurality of rectification circuits, and a reference signal; and a storage circuit configured to store a pre-select signal provided from an external system, and to output a stored signal to each of the plurality of rectification circuits as the plurality of second control signals.

A voltage generation circuit includes a plurality of rectification circuits configured to be selectively activated depending on a plurality of first control signals, and to generate an internal voltage according to respective reference voltages capable of being independently trimmed depending on a plurality of second control signals; a detection circuit configured to generate a detection signal by comparing a pre-detection signal, generated in each of the plurality of rectification circuits, and a reference signal; and a storage circuit configured to store a pre-select signal provided from an external system, and to output a stored signal to each of the plurality of rectification circuits as the plurality of second control signals.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A wave shaping circuit reduces slope magnitudes during increasing and decreasing voltage transitions. The wave shaping circuit includes a first switch that receives an input voltage having at least two voltage values where an input voltage transition between the at least two voltage values has a first slope magnitude; an inductor connected in series with the first switch; a second switch connected in a parallel arrangement with the first switch and the inductor; and a capacitor having a first end connected between the inductor and an output port and a second end connected to ground. When the input voltage begins the input voltage transition to a higher voltage value, the first switch turns on and the second switch turns off, such that the inductor limits current flow from the input voltage, decreasing a second slope magnitude of an output voltage transition to less than the first slope magnitude.

A wave shaping circuit reduces slope magnitudes during increasing and decreasing voltage transitions. The wave shaping circuit includes a first switch that receives an input voltage having at least two voltage values where an input voltage transition between the at least two voltage values has a first slope magnitude; an inductor connected in series with the first switch; a second switch connected in a parallel arrangement with the first switch and the inductor; and a capacitor having a first end connected between the inductor and an output port and a second end connected to ground. When the input voltage begins the input voltage transition to a higher voltage value, the first switch turns on and the second switch turns off, such that the inductor limits current flow from the input voltage, decreasing a second slope magnitude of an output voltage transition to less than the first slope magnitude.

A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.