Embodiments of the present invention provide for a core stage in an application-specific integrated circuit core which drives both a clock pulse signal and a clock pulse negative/complement signal concurrently, thereby resulting in perfectly aligned signals. The core stage can include a pulse generator, a clock distribution circuit, and a set of latches.

Embodiments of the present invention provide for a core stage in an application-specific integrated circuit core which drives both a clock pulse signal and a clock pulse negative/complement signal concurrently, thereby resulting in perfectly aligned signals. The core stage can include a pulse generator, a clock distribution circuit, and a set of latches.

A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.

A device is provided for jamming electromagnetic radiation liable to be emitted by at least one portion of an interconnect region located above at least one zone of an integrated electronic circuit produced in and on a semiconductor substrate. The device includes an antenna located above the at least one zone of the circuit and generating circuit coupled to the antenna and configured to generate an electrical signal having at least one pseudo-random property to pass through the antenna.

A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.

A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.

A phase shift circuitry includes: a signal generation circuitry that receives an input signal, and outputs four signals different in phase from each other by 90 degrees based on the input signal, the four signals includes a first signal and a second signal; four variable amplifier circuitry that each includes a transistor, and amplify the four signals individually, with amplification factors based on control voltages supplied to gates of the transistors, the four variable amplifier circuitry include a first amplifier amplifies the first signal by a first control voltage and a second amplifier amplifies the second signal by a second control voltage; a synthetic circuitry that synthesizes output signals of the four variable amplifier circuitry, and outputs a synthesized signal; and a control circuitry supplies voltages, that are equal to or higher than the gate threshold value, to the first amplifier and the second amplifier.

A phase shift circuitry includes: a signal generation circuitry that receives an input signal, and outputs four signals different in phase from each other by 90 degrees based on the input signal, the four signals includes a first signal and a second signal; four variable amplifier circuitry that each includes a transistor, and amplify the four signals individually, with amplification factors based on control voltages supplied to gates of the transistors, the four variable amplifier circuitry include a first amplifier amplifies the first signal by a first control voltage and a second amplifier amplifies the second signal by a second control voltage; a synthetic circuitry that synthesizes output signals of the four variable amplifier circuitry, and outputs a synthesized signal; and a control circuitry supplies voltages, that are equal to or higher than the gate threshold value, to the first amplifier and the second amplifier.

A time synchronization device adapted for an electronic apparatus, an electronic apparatus, a time synchronization system and a time synchronization method. The time synchronization device includes: a signal generating circuit and a time adjusting circuit. The signal generating circuit includes: a control circuit, configured to generate a frequency control word; and a signal adjusting circuit, configured to receive the frequency control word and an input signal having an initial frequency, and to generate and output an output signal having a target frequency based on the frequency control word and the input signal. The time adjusting circuit is configured to perform a synchronization adjusting operation on a clock signal of the electronic apparatus based on the output signal having the target frequency.

A time synchronization device adapted for an electronic apparatus, an electronic apparatus, a time synchronization system and a time synchronization method. The time synchronization device includes: a signal generating circuit and a time adjusting circuit. The signal generating circuit includes: a control circuit, configured to generate a frequency control word; and a signal adjusting circuit, configured to receive the frequency control word and an input signal having an initial frequency, and to generate and output an output signal having a target frequency based on the frequency control word and the input signal. The time adjusting circuit is configured to perform a synchronization adjusting operation on a clock signal of the electronic apparatus based on the output signal having the target frequency.