A fixed time-delay circuit of a high-speed interface is disclosed. The fixed time-delay circuit comprises: a counter circuit for generating a shift selection signal of any bit; a data selector circuit for receiving first parallel data signals and rearranging the first parallel data signals according to the shift selection signal and a first low-speed clock to obtain second parallel data signals; a clock selector circuit for selecting, according to the shift selection signal, one clock from multiple input clocks having different phases, for outputting, to form a second low-speed clock; and a synchronization circuit for synchronizing the second parallel data signals according to the second low-speed clock. According to the circuit, initialization alignment among multichannel data of the high-speed interface can be achieved.

A drive circuit of a voltage-controlled power semiconductor element, including first to fourth switching elements, first and second delay circuits, an overcurrent detection circuit, a slow shutdown detection circuit and a flip-flop. The first switching element turns on upon receiving an off signal. The second switching element is turned on by the first delayed signal generated by the first delay circuit. The third switching element turns on upon receiving a second delayed signal generated by the second delay circuit through the flip-flop. The fourth switching element is turned on by the slow shutdown detection signal generated by the slow shutdown detection circuit. The first to fourth switching elements extract electric charges from the gate terminal of the voltage-controlled power semiconductor element, with first to fourth extracting capabilities, respectively. The first and fourth extracting capabilities are larger than the third extracting capability and smaller than the second extracting capability.

A transmitter circuit applicable to a digital isolator is provided, adapted to receive a data input signal and coupled to an isolation barrier, developing a receiver input signal to a receiver circuit for generating a data output signal. The transmitter circuit generates a transmitter output signal in response to a rising edge and falling edge of the data input signal, and includes a rising and falling converter for outputting a converted data input signal according to the rising edge and falling edge of the data input signal, a delay and logic unit for receiving the converted data input signal and generating a carrier signal, and an AND gate receiving the converted data input signal and the carrier signal, and outputting the transmitter output signal. Since a number of pulses of the carrier signal is limited and definite, the present invention achieves to reduce power consumption and electromagnetic interferences effectively.

Disclosed is a system and method for power line control of electrical fans. The system generates a sinusoidal wave using a crystal oscillator. Control information is added to the sinusoidal wave by routing the wave through a phase inversion circuit a predetermined intervals according to a protocol. The resulting control signal is sent on a power line. The control signal is received using a crystal filter, decoded and converted to executable instructions for controlling a fan motor.

Disclosed is a system and method for power line control of electrical fans. The system generates a sinusoidal wave using a crystal oscillator. Control information is added to the sinusoidal wave by routing the wave through a phase inversion circuit a predetermined intervals according to a protocol. The resulting control signal is sent on a power line. The control signal is received using a crystal filter, decoded and converted to executable instructions for controlling a fan motor.

A monitoring device includes: an acquisition unit for acquiring a clock signal output from a communication circuit that outputs the clock signal; and a monitoring unit for analyzing the waveform of the clock signal acquired by the acquisition unit, based on a predetermined reference clock signal having a period equal to or shorter than a period of the clock signal to thereby determine whether or not there is a sign of malfunction in the communication circuit.

Systems, devices, computer-implemented methods, and/or computer program products that facilitate low power, wideband multitone generation. In one example, a multitone generator device can comprise a controller operatively coupled to first and second digital-to-analog converters (DACs). The controller can apply different delays of a sampling signal to the first and second DACs to facilitate sideband suppression of signals output by the first and second DACs. One aspect of such a multitone generator device is that the multitone generator device can facilitate low power, wideband multitone generation.

Systems, devices, computer-implemented methods, and/or computer program products that facilitate low power, wideband multitone generation. In one example, a multitone generator device can comprise a controller operatively coupled to first and second digital-to-analog converters (DACs). The controller can apply different delays of a sampling signal to the first and second DACs to facilitate sideband suppression of signals output by the first and second DACs. One aspect of such a multitone generator device is that the multitone generator device can facilitate low power, wideband multitone generation.

An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.

An oscillator includes first and second capacitors, an inverter, a voltage shifting circuit, and a hysteresis buffer. The first and second capacitors have first terminals adapted to be coupled to respective first and second nodes, and second terminals coupled to ground. The inverter has an input coupled to the first node, and an output coupled to the second node. The voltage shifting circuit is coupled to the first and second nodes and has an input for receiving a tuning signal. The voltage shifting circuit changes an average voltage at the first node according to the tuning signal when an oscillation occurs in response to a crystal being coupled between the first and second nodes. The hysteresis buffer has an input coupled to one of first node and the second node, and an output for providing a clock signal having a duty cycle responsive to the tuning signal.