A current regulator circuit to improve electromagnetic compatibility performance operation of an IC device includes an input to receive a regulated voltage signal, an output to provide an output voltage at a desired voltage level, the output voltage exhibiting noise from a load, a first field effect transistor FET including a first source electrode coupled to the input, a first drain electrode coupled to the output, and a first gate electrode, a voltage clamp circuit coupled to the output, the voltage clamp circuit configured to conduct a varying current based upon the noise, a constant current source to provide a constant current, and a second FET including a second source electrode coupled to the output, a second drain electrode coupled to the constant current source and to the first gate electrode, and a second gate electrode coupled to the voltage clamp circuit to mirror the varying current in the second FET.

A driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. A second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. Logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. A sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. The non-overlap time overlaps in time with the total deglitch time.

A current regulator circuit to improve electromagnetic compatibility performance operation of an IC device includes an input to receive a regulated voltage signal, an output to provide an output voltage at a desired voltage level, the output voltage exhibiting noise from a load, a first field effect transistor FET including a first source electrode coupled to the input, a first drain electrode coupled to the output, and a first gate electrode, a voltage clamp circuit coupled to the output, the voltage clamp circuit configured to conduct a varying current based upon the noise, a constant current source to provide a constant current, and a second FET including a second source electrode coupled to the output, a second drain electrode coupled to the constant current source and to the first gate electrode, and a second gate electrode coupled to the voltage clamp circuit to mirror the varying current in the second FET.

A current regulator circuit to improve electromagnetic compatibility performance operation of an IC device includes an input to receive a regulated voltage signal, an output to provide an output voltage at a desired voltage level, the output voltage exhibiting noise from a load, a first field effect transistor FET including a first source electrode coupled to the input, a first drain electrode coupled to the output, and a first gate electrode, a voltage clamp circuit coupled to the output, the voltage clamp circuit configured to conduct a varying current based upon the noise, a constant current source to provide a constant current, and a second FET including a second source electrode coupled to the output, a second drain electrode coupled to the constant current source and to the first gate electrode, and a second gate electrode coupled to the voltage clamp circuit to mirror the varying current in the second FET.

An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.

An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.

Aspects of the present disclosure provide techniques and apparatus for current-mode analog signal filtering. An example filter circuit generally includes a current-mode amplifier. The current-mode amplifier includes a first amplifier including an input and an output; a first inverter including an input coupled to the output of the first amplifier and including an output coupled to a first feedback path, the first feedback path being coupled to a first input of the filter circuit; and a second inverter including an input coupled to the output of the first amplifier.

Aspects of the present disclosure provide techniques and apparatus for current-mode analog signal filtering. An example filter circuit generally includes a current-mode amplifier. The current-mode amplifier includes a first amplifier including an input and an output; a first inverter including an input coupled to the output of the first amplifier and including an output coupled to a first feedback path, the first feedback path being coupled to a first input of the filter circuit; and a second inverter including an input coupled to the output of the first amplifier.

The present invention provides an integrated circuit with a multiplexed pin and a pin multiplexing method. The multiplexed pin of the integrated circuit extends out with two connecting ends to receive two logic level signals which are finally restored in a chip. A first signal input end receives a signal representing whether to enable or disable, a second signal input end receives a function signal which achieves a certain function, and a diode, a resistor, and a first current source are used together to achieve multiplexing of the pin based on turn-on and clamping characteristics of the diode. The number of pins to be packaged and the area occupied by a chip on board are reduced, which is conducive to a small package design of the chip.

The present invention provides an integrated circuit with a multiplexed pin and a pin multiplexing method. The multiplexed pin of the integrated circuit extends out with two connecting ends to receive two logic level signals which are finally restored in a chip. A first signal input end receives a signal representing whether to enable or disable, a second signal input end receives a function signal which achieves a certain function, and a diode, a resistor, and a first current source are used together to achieve multiplexing of the pin based on turn-on and clamping characteristics of the diode. The number of pins to be packaged and the area occupied by a chip on board are reduced, which is conducive to a small package design of the chip.