An electronic comparison circuit can identify at least three conditions of an input signal received by the electronic comparison circuit. A first one of the at least three conditions occurs when a value of the input signal is less than a first threshold value, a second one of the at least three conditions occurs when a value of the input signal is greater than the first threshold value and less than a second threshold value, and a third one of the at least three conditions occurs when a value of the input signal is greater than the second threshold value. A magnetic field sensor can use the electronic comparison circuit.

An electronic comparison circuit can identify at least three conditions of an input signal received by the electronic comparison circuit. A first one of the at least three conditions occurs when a value of the input signal is less than a first threshold value, a second one of the at least three conditions occurs when a value of the input signal is greater than the first threshold value and less than a second threshold value, and a third one of the at least three conditions occurs when a value of the input signal is greater than the second threshold value. A magnetic field sensor can use the electronic comparison circuit.

A signal transmission circuit includes a primary element configured to receive differential signals which are generated from a transmission signal and contain alternating-current (AC) components, a secondary element magnetically or capacitively coupled with the primary element and configured to output AC signals containing the AC components of the differential signals, a secondary circuit including a pair of transmission lines configured to propagate the AC signals. The secondary circuit is electrically connected to the secondary element and extracts the transmission signal from the AC signals. The feedback circuit feedbacks an intermediate voltage between voltages of the pair of transmission lines such that the intermediate voltage is converged to a reference voltage. This signal transmission circuit prevents the secondary circuit from malfunctioning due to noise.

A signal transmission circuit includes a primary element configured to receive differential signals which are generated from a transmission signal and contain alternating-current (AC) components, a secondary element magnetically or capacitively coupled with the primary element and configured to output AC signals containing the AC components of the differential signals, a secondary circuit including a pair of transmission lines configured to propagate the AC signals. The secondary circuit is electrically connected to the secondary element and extracts the transmission signal from the AC signals. The feedback circuit feedbacks an intermediate voltage between voltages of the pair of transmission lines such that the intermediate voltage is converged to a reference voltage. This signal transmission circuit prevents the secondary circuit from malfunctioning due to noise.

A device voltage shifter includes a first voltage reference node, a second voltage reference node, an output node and a clamp node. A first high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node. A second high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node. A third high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node. A voltage regulator of the voltage shifter is coupled between the output node and the clamp node.

A device voltage shifter includes a first voltage reference node, a second voltage reference node, an output node and a clamp node. A first high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node and a second conduction terminal coupled to the clamp node. A second high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the clamp node and a second conduction terminal coupled to the second voltage reference node. A third high-voltage switching transistor of the voltage shifter has a first conduction terminal coupled to the first voltage reference node, a control terminal coupled to the clamp node, and a second conduction terminal coupled to the output node. A voltage regulator of the voltage shifter is coupled between the output node and the clamp node.

Disclosed is an apparatus and a method for facilitating a first frequency filtering and a second frequency filtering together with nonreciprocal frequency conversion for electromagnetic isolation.

Disclosed is an apparatus and a method for facilitating a first frequency filtering and a second frequency filtering together with nonreciprocal frequency conversion for electromagnetic isolation.

An I2C wake-up circuit, method and electronic device are disclosed. The I2C wake-up circuit includes: a clock wake-up circuit, configured to send a clock wake-up signal to a clock circuit in response to detecting a start signal on a serial clock line SCL and a serial data line SDA; and a signal hold circuit, configured to hold the serial data line SDA in a state of not transmitting address information until a clock signal sent by the clock circuit that is wake-up is received. The present I2C wake-up solution can realize normal data reception through a simple hardware circuit without a specific address wake-up and maximize power saving by turning on the clock when there is access and turning off the clock when the access ends.

An I2C wake-up circuit, method and electronic device are disclosed. The I2C wake-up circuit includes: a clock wake-up circuit, configured to send a clock wake-up signal to a clock circuit in response to detecting a start signal on a serial clock line SCL and a serial data line SDA; and a signal hold circuit, configured to hold the serial data line SDA in a state of not transmitting address information until a clock signal sent by the clock circuit that is wake-up is received. The present I2C wake-up solution can realize normal data reception through a simple hardware circuit without a specific address wake-up and maximize power saving by turning on the clock when there is access and turning off the clock when the access ends.