An electronic system is disclosed. The system has a differential signal generator configured to generate first and second single ended signals having opposite polarities. The input signal, and the first and second single ended signals transition between a first power voltage and a first ground voltage. The system also has a glitch management circuit configured to generate an output signal based on the first and second single ended signals, where the output signal transitions between a second power voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single ended signals, and to generate first and second intermediate signals. The first and second intermediate signals each transition between the second power voltage and the second ground voltage. The system also has a second latch configured generate the output signal based on the first and second intermediate signals.

An electronic system is disclosed. The system has a differential signal generator configured to generate first and second single ended signals having opposite polarities. The input signal, and the first and second single ended signals transition between a first power voltage and a first ground voltage. The system also has a glitch management circuit configured to generate an output signal based on the first and second single ended signals, where the output signal transitions between a second power voltage and a second ground voltage. The glitch management circuit includes a first latch configured to receive the first and second single ended signals, and to generate first and second intermediate signals. The first and second intermediate signals each transition between the second power voltage and the second ground voltage. The system also has a second latch configured generate the output signal based on the first and second intermediate signals.

A circuit for suppressing electromagnetic interference signal on power lines. The circuit includes a first sensing circuit, a first amplifier, and a first controlled signal source. The first sensing circuit is arranged to sense a first electromagnetic interference signal. The first amplifier is arranged to be powered by a power source. The first amplifier provides a first amplification factor and being operably connected with the first sensing circuit to amplify a signal sensed by the first sensing circuit. The first controlled signal source provides a second amplification factor and is operably connected with the first amplifier to regulate or further amplify the amplified signal to provide a first suppression signal that reduces the first electromagnetic interference signal. Multiple such circuits can be cascaded to form a mufti-stage electromagnetic interference suppression circuit.

Systems, methods, and computer program product embodiments are disclosed for performing electrophysiology (EP) signal processing. An embodiment includes an electrocardiogram (ECG) circuit board configured to process an ECG signal. The embodiment further includes a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal. The ECG circuit board and the plurality of IC circuit boards share substantially a same circuit configuration and components. The ECG circuit board further processes the ECG signal using substantially a same path as each IC circuit board uses to process its corresponding IC signal.

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.

Various implementations described herein are directed to a device having alarm circuitry that receives a clock signal and provides alarm chain signals based on the clock signal. The device may include delay chain circuitry that receives the alarm chain signals from the alarm circuitry and provides delay chain signals. The device may include output circuitry that receives the delay chain signals from the delay chain circuitry and provides an alarm control signal based on the delay chain signals.

A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

A circuit to generate complementary signals comprises a first string of inverters with two inverters in series to produce a true signal in response to an input signal, and a second string of inverters with three inverters in series to produce a complement signal in response to the input signal. A compensation capacitance circuit is connected to a node in the first string of inverters. The compensation capacitance circuit can add capacitance to the node to increase a resistance-capacitance RC delay at the node in a manner which emulates the delay across PVT conditions an inverter in the second string of inverters.

A circuit to generate complementary signals comprises a first string of inverters with two inverters in series to produce a true signal in response to an input signal, and a second string of inverters with three inverters in series to produce a complement signal in response to the input signal. A compensation capacitance circuit is connected to a node in the first string of inverters. The compensation capacitance circuit can add capacitance to the node to increase a resistance-capacitance RC delay at the node in a manner which emulates the delay across PVT conditions an inverter in the second string of inverters.