Logic circuitry includes a first logic circuit, second logic circuits, a third logic circuit, and fourth logic circuits. The first logic circuit inverts a first output signal relative to an input signal only in response to a first control signal having a first state that indicates that the input signal has remained in a same logic state for at least a predefined period of time. The second logic circuits are coupled in series. The second logic circuits generate a second output signal in response to the first output signal. The third logic circuit inverts a third output signal relative to the second output signal only in response to the first control signal having the first state. The fourth logic circuits are coupled in series. The fourth logic circuits generate a fourth output signal in response to the third output signal.

Various NLTL frequency comb generator embodiments are disclosed for broadband impedance matching to generate an output signal comprising broadband harmonics of an input signal. The NLTL frequency comb generator comprises a plurality of segments cascaded in series, with each segment comprising a series inductor and a non-linear shunt capacitor. The non-linear shunt capacitor may couple to corresponding series inductors in the same polarity. A broadband biasing circuit feeds a DC bias or DC ground to the non-linear shunt capacitors for broadband input and output impedance matching. The broadband biasing circuit may be a low pass filter to prevent RF signal from leaking through the biasing circuit. The NLTL frequency comb generator, the broadband biasing circuit, and an output DC blocking capacitor may be integrated in a single chip in a compact packaging to achieve a broadband input/output impedance matching without relying on external lumped matching components.

Various NLTL frequency comb generator embodiments are disclosed for broadband impedance matching to generate an output signal comprising broadband harmonics of an input signal. The NLTL frequency comb generator comprises a plurality of segments cascaded in series, with each segment comprising a series inductor and a non-linear shunt capacitor. The non-linear shunt capacitor may couple to corresponding series inductors in the same polarity. A broadband biasing circuit feeds a DC bias or DC ground to the non-linear shunt capacitors for broadband input and output impedance matching. The broadband biasing circuit may be a low pass filter to prevent RF signal from leaking through the biasing circuit. The NLTL frequency comb generator, the broadband biasing circuit, and an output DC blocking capacitor may be integrated in a single chip in a compact packaging to achieve a broadband input/output impedance matching without relying on external lumped matching components.

Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.

In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.

The present disclosure provides a signal converting circuit including a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert multiple input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of multiple bit configurations of the digital signal. The reference information is relevant to a change of the phase interpolator circuit due to a manufacture process variation.

This document describes systems and techniques for adaptive frequency control in integrated circuits. In response to operating conditions that permit a lower frequency of a clock signal, the described systems and techniques dynamically reduce the clock frequency without adjusting the frequency of an input clock signal. The clock frequency is decreased by gating a fraction of the input clock signal and stretching the ungated cycles by an offset amount. By dynamically adjusting the clock frequency in this manner, an integrated circuit can change its clock frequency more quickly and maintain the supply voltage closer to a lower voltage limit to reduce power consumption and allow safer operations.

A phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates first and second thermometer codes and a selection signal based on a code. The DAC includes unit cells, determines two of weight signals as first and second target weight signals based on the selection signal, and adjusts a current of the first and second target weight signals by controlling the unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of input clock signals as first and second target clock signals and generates an output clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the output clock signal is between phases of the first and second target clock signals. The unit cells include different first and second unit cells.