Aspects of the technology described herein relate to ultrasound device circuitry as may form part of a single substrate ultrasound device having integrated ultrasonic transducers. The ultrasound device circuitry may facilitate the generation of ultrasound waveforms in a manner that is power- and data-efficient.

Aspects of the technology described herein relate to ultrasound device circuitry as may form part of a single substrate ultrasound device having integrated ultrasonic transducers. The ultrasound device circuitry may facilitate the generation of ultrasound waveforms in a manner that is power- and data-efficient.

A numerical information generating apparatus receives information of a programmable logic integrated circuit that includes a plurality of crossbar switches each including resistance change elements, calculates, for each of the plurality of crossbar switches, a base delay that is a delay in which influence of a load capacitance of other crossbar switch is excluded and a correction delay that is a delay caused by influence of a fanout of other crossbar switch, and further calculates a delay of each of the plurality of crossbar switches based on the base delay and the correction delay corresponding to each of the plurality of crossbar switches.

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

A clock driver circuit for low powered clock driving may include: a multiple phase divider; a buffer supplying at least one of multiple phases to the multiple phase divider at a center frequency that is an integer multiple of an input frequency; and wherein the multiple phase divider and the buffer share a same current from a supply rail.

Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.

A delay circuit includes a voltage/current conversion unit, a capacitor, and an output logic unit. The voltage/current conversion unit receives an input signal and generates current based on a voltage level of the input signal, and the generated current is proportional to the voltage level of the input signal. The capacitor is electrically connected to the voltage/current conversion unit and configured to receive the current generated by the voltage/current conversion unit, to charge. The output logic unit is electrically connected to the capacitor configured to receive a voltage signal on a terminal of the capacitor and generate an output signal based on the voltage signal, a delay time between a transition time point of the input signal and a transition time point of the output signal is not related to the voltage level of the input signal.

A delay circuit includes a voltage/current conversion unit, a capacitor, and an output logic unit. The voltage/current conversion unit receives an input signal and generates current based on a voltage level of the input signal, and the generated current is proportional to the voltage level of the input signal. The capacitor is electrically connected to the voltage/current conversion unit and configured to receive the current generated by the voltage/current conversion unit, to charge. The output logic unit is electrically connected to the capacitor configured to receive a voltage signal on a terminal of the capacitor and generate an output signal based on the voltage signal, a delay time between a transition time point of the input signal and a transition time point of the output signal is not related to the voltage level of the input signal.

There is disclosed herein programmable delay lines and control methods having glitch suppression. In particular, the programmable delay lines may include latches that are triggered based on a trigger event of an input signal (which is often an edge of the input signal). The programmable delay lines may include one or more latches coupled between capacitor and transistor subassemblies and the latches, where the latches cause a delay between the time the trigger event arrives at the capacitor and transistor subassemblies and the latches. The delay can prevent the latches from updating at the same time that the edge of the input signal arrives at the capacitor and transistor subassemblies, which can suppress glitches that can causes errors in operation.