Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.

In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally-staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal.

A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal.

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Some embodiments include a plasma system comprising: a plasma chamber, an RF plasma generator, a bias generator, and a controller. The RF plasma generator may be electrically coupled with the plasma chamber and may produce a plurality of RF bursts, each of the plurality of RF bursts including RF waveforms, each of the plurality of RF bursts having an RF burst turn on time and an RF burst turn off time. The bias generator may be electrically coupled with the plasma chamber and may produce a plurality of bias bursts, each of the plurality of bias bursts including bias pulses, each of the plurality of bias bursts having an bias burst turn on time and an bias burst turn off time. In some embodiments the controller is in communication with the RF plasma generator and the bias generator that controls the timing of various bursts or waveforms.

In one example, a device may include a first push-pull driver with a first impedance and a push-pull driver unit with a second push-pull driver having a second impedance. The push-pull driver unit may be in parallel with the first push-pull driver. The device may further include a pulse generating unit to activate the push-pull driver unit for a delay time following an edge transition in an input signal. In one example, the device may have an output impedance that is less than the first impedance when the push-pull driver unit is activated.

In one example, a device may include a first push-pull driver with a first impedance and a push-pull driver unit with a second push-pull driver having a second impedance. The push-pull driver unit may be in parallel with the first push-pull driver. The device may further include a pulse generating unit to activate the push-pull driver unit for a delay time following an edge transition in an input signal. In one example, the device may have an output impedance that is less than the first impedance when the push-pull driver unit is activated.