On the basis of the peak point of the integrated waveform of the reception signal for each one-bit time, a timing of resetting the integrated value of the reception signal for each one-bit time and a timing of determining whether a voltage of the reception signal for each one-bit time is high or low are indicated.

A transmitter device having a calibrator circuit is disclosed. The calibrator circuit performs duty cycle calibration and phase calibration on a plurality of clock signals of the transmitter device. In one embodiment, the phase calibration is performed based on a comparison of the clock signals to a reference clock signal from the plurality of clock signals. In another embodiment, the calibrator circuit uses fixed patterns of data signals to perform phase calibration on the plurality of clock signals.

A signal output circuit and a circuit for outputting a delayed signal are provided. The signal output circuit includes: a first control subcircuit, configured to receive a first pulse signal and an input signal and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control subcircuit configured to receive a second pulse signal and the input signal and output a second adjustment signal; and the signal output subcircuit is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal.

A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.

Various embodiments relate to an amplitude shift keying (ASK) demodulator for demodulating an input signal, including: a frequency filter configured to receive the input signal, wherein the frequency filter includes adjustable components configured to adjust the frequency response of the frequency filter; a rectifier configured to rectify an output of the frequency filter, wherein the rectifier includes an adjustable current source configured to adjust the current consumption of the rectifier; a reference signal generator configured to produce a reference signal; a current to voltage converter configured to convert the current of the rectified signal to a rectified voltage and to convert the current of the reference signal to a reference voltage; and a comparator configured to compare the rectified voltage to the reference voltage and to produce a demodulated output signal.

A phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal, the PI stage being further configured to avoid a pull-up/pull-down (PUPD) short-circuit situation by using the multi-bit weighting signal and a logical inverse thereof (multi-bit weighting_bar signal); and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component; the capacitive component being tunable; and the capacitive component having a Miller effect configuration resulting in a reduced footprint of the amplifying stage.

The present disclosure relates to a memory device for correcting a pulse duty ratio and a memory system including the same, and relates to a memory device which corrects the duty ratio of a primary pulse of a memory device control signal, and a memory system including the same.

The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.