An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

A first flipflop outputs a first signal synchronized with a first clock signal, a second flipflop outputs a second signal synchronized with a second clock signal, and a third flipflop outputs a third signal synchronized with a third clock signal. The second flipflop includes first to fifth transistors. In the first transistor, the second clock signal is input to a first terminal and the second signal is output from a second terminal. In the second transistor, a first signal is input to a first terminal, a second terminal is electrically connected to a gate of the first transistor, and the first clock signal is input to a gate. In the third transistor, the third signal is input to a first terminal, a second terminal is electrically connected to the gate of the first transistor, and the third clock signal is input to a gate.

A circuit includes a filter, a comparator, and converter. A first input of the comparator couples to the output of the filter. A second input of the comparator is configured to receive ramp signal. An input of the converter couples to the output of the comparator. The circuit also includes a dual minimum pulse generator having an input coupled to the output of the converter. The dual minimum pulse generator is configured to, responsive to an input pulse on the input of the dual minimum pulse generator having a pulse width less than a predetermined delay time period, generate a pulse on the first output of the dual minimum pulse generator that has a pulse width equal to a sum of the pulse width of the input pulse and the predetermined delay time period. A driver is coupled to the output of the dual minimum pulse generator.

A multi-phase clock generator circuit includes a phase reference generator circuit configured to generate a phase reference signal in response to a phase selection signal and a peak ramp signal. A phase error correction circuit is configured to provide an error signal based on a synchronization clock signal and a multi-phase clock signal. The error signal is applied to the phase reference signal to correct for phase errors in the multi-phase clock signal. A comparator is configured to compare a ramp signal and the phase reference signal to produce the multi-phase clock signal.

Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.

Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

Embodiments of the disclosure are drawn to apparatuses and methods for transmission beamforming. A multiphase beam steering transmitter may include a transmitter array of multiple transmitters. A transmitter may include a multiphase logic decoder that directly controls a power amplifier to perform a vector addition of a beam phase and amplitude. A transmitter of the array may include a multiphase clock generator that outputs basis phases with embedded phase modulation data which are output to the multiphase logic decoder. The multiphase clock generator may receive a modulated clock signal. The PA may be a multiphase switched capacitor power amplifier. The multiphase logic decoder may output two phases adjacent to a desired phase as inputs to clocks of the SCPA. The multiphase logic decoder may further output a control signal that determines which cells in the SCPA are activated and when.

A passable latch circuit and variable delay chains built with one or more passable latch circuits are disclosed. The passable latch circuit has a dynamic latch including a first P-transistor, a first N-transistor, a second P-transistor, a second N-transistor and a clock input circuitry. The passable latch circuit further includes a control switch connected between the gates of the second P-transistor and the second N-transistor. The control switch has an on state and an off state, and the passable latch circuit is configured to have different delays by controlling the state of the control switch.

A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADCs, an open-loop clocking circuit, and a time-multiplexing circuit. The plurality of ADCs receive an analog input signal. Each ADC is configured to sample the analog input signal upon receipt of a respective clock signal. The open-loop clocking circuit receives a main clock signal having a reference frequency, and then divides the main clock signal into a sequential plurality of respective clock signals, each having a frequency lower than the reference frequency, and each triggered by one other respective clock signal starting from the main clock signal. The open-loop clocking circuit then distributes the plurality of respective clock signals to the plurality of ADCs. The time-multiplexing circuit is coupled to the plurality of ADCs and is configured to combine respective digital output signals from the plurality of ADCs into a time series.