Methods and apparatus for time-to-digital conversion. An example apparatus includes a first input; a second input; a delay line coupled to the first input and comprising a plurality of first delay elements coupled in series, each of the plurality of first delay elements having a first delay time; a second delay element having an input coupled to the second input and having the first delay time; a third delay element having an input coupled to the second input and having a second delay time, the second delay time being smaller than the first delay time; a first set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the second delay element; and a second set of arbiters having first inputs coupled to the delay line and having second inputs coupled to an output of the third delay element.

A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.

A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit includes a control circuit, a signal generation circuit, and a duty cycle adjustment circuit. The duty cycle adjustment circuit is configured to generate a target voltage having a duty cycle that is equal to a target duty cycle, the control circuit is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit is configured to receive the target voltage and the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the target voltage and the frequency control word, and the spread spectrum output signal corresponds to the frequency control word and a duty cycle of the spread spectrum output signal is the target duty cycle.

Novel unipolar circuits and vertical structures are described which exhibit low stand-by power, low dynamic power, high speed performance, and have higher density compared to conventional silicon CMOS circuitry. In one embodiment, a design methodology utilizing either a p-channel or n-channel transistor type such that each logic gate is clocked and the clocking mechanism provides the pull up or pull down. Further embodiments include novel designs of vertical unipolar logic gates which provides for high density. Ultra-short transistor channel lengths in vertical unipolar logic gates are fabricated with a deposition processin lieu of a lithography processthereby providing for high speed operation and low cost manufacturing.

A semiconductor device may include a fuse array configured to output fuse data. The semiconductor device may include a latch circuit configured to store the fuse data during an enabled section of a dummy boot-up signal, output the stored fuse data as a fuse data information signal during a disabled section of the dummy boot-up signal, and fix the fuse data information signal to a specific level during the enabled section of the dummy boot-up signal regardless of the stored fuse data.

A semiconductor device configured by bonding a first and a second chip together, including: a first signal output circuit provided at both the first and the second chip and driven by a first drive power; a second signal output circuit provided at both the first and the second chip and driven by a second drive power; a first phase comparison circuit, provided at the first chip, that compares a phase of a first signal and a second signal; a second phase comparison circuit that is provided at the second chip, and that compares a phase of a third signal and a fourth signal; a third phase comparison circuit, provided at the first chip, that compares a phase of a fifth signal and a sixth signal; and a fourth phase comparison circuit, provided at the second chip, that compares a phase of a seventh signal and an eighth signal.

Aspects of this disclosure relate to adjusting a phase of a clock signal provided to a device based on a feedback signal from the device. The feedback signal can provide phase information associated with the device and/or other information associated with the device, such as temperature information. A feedback signal processor can compute a phase control signal based on the feedback signal. The phase control signal can be used to adjust the phase of the clock signal. By adjusting the phase of one or more clock signals, several devices, such as data converters, can be synchronized.

A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.

A compensated comparator is provided, including a decision stage and a differential stage provided with two transistors connected by their sources, the differential stage being provided with compensation means to compensate the effects of a dispersion of the threshold voltages of the transistors forming the differential stage, the compensation means including first and second capacitors each connected to a gate of one of the two transistors, and being configured to memorize a voltage that is a function of a threshold voltage of the considered transistors.

The present technology relates to a signal processing apparatus and method capable of increasing a harmonic rejection ratio while suppressing an increase in power consumption. In one aspect of the present technology, two local signals having a 1/3 duty ratio and phases mutually shifted by a 1/2 period are mixed with each signal of a differential signal, and a difference between results of the mixing of the two local signals is calculated. The present technology can be applied to, for example, a signal processing apparatus, a transmission apparatus, a reception apparatus, a communication apparatus, an electronic apparatus having a transmission function, a reception function, or a communication function, or a computer that controls those apparatuses.