A semiconductor device includes clock adjustment circuits, provided to a plurality of functional circuits operating in synchronization with a clock signal respectively for adjusting a delay amount for each functional circuit, and a clock path selection circuit for controlling whether a clock is transmitted to the functional circuits through any one of a plurality of paths included in the clock adjustment circuits respectively. In the semiconductor device, the clock path selection circuit outputs a path instruction signal for instructing switching of a path for transmitting a clock signal in accordance with a change in an operation state of a plurality of functional circuits.

A semiconductor device includes clock adjustment circuits, provided to a plurality of functional circuits operating in synchronization with a clock signal respectively for adjusting a delay amount for each functional circuit, and a clock path selection circuit for controlling whether a clock is transmitted to the functional circuits through any one of a plurality of paths included in the clock adjustment circuits respectively. In the semiconductor device, the clock path selection circuit outputs a path instruction signal for instructing switching of a path for transmitting a clock signal in accordance with a change in an operation state of a plurality of functional circuits.

A signal output circuit and a circuit for outputting a delayed signal are provided. The signal output circuit includes: a first control subcircuit, configured to receive a first pulse signal and an input signal and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control subcircuit configured to receive a second pulse signal and the input signal and output a second adjustment signal; and the signal output subcircuit is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal.

A signal output circuit and a circuit for outputting a delayed signal are provided. The signal output circuit includes: a first control subcircuit, configured to receive a first pulse signal and an input signal and output a first adjustment signal, a first preset edge of the first adjustment signal has a first delay relative to a rising edge of the input signal; a second control subcircuit configured to receive a second pulse signal and the input signal and output a second adjustment signal; and the signal output subcircuit is configured to receive the first adjustment signal and the second adjustment signal, and output a delayed output signal, a rising edge of the delayed output signal is generated according to the first preset edge of the first adjustment signal, and a falling edge of the delayed output signal is generated according to the second preset edge of the second adjustment signal.

An example apparatus includes: a first level shifting circuit including a supply output; a first deserializer stage including a supply input, a first input, a first output, and a second output, the supply input coupled to the supply output; a second level shifting circuit including a second input and a third output, the second input coupled to the first output; and a second deserializer stage including a third input, a fourth output and a fifth output, the third input coupled to the third output.

A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.

A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

A pulse generation circuit and stagger pulse generation circuit are provided. The pulse generation circuit includes: an oscillation circuit that receives a control signal and generates a first oscillation signal according to the control signal; a period adjustment circuit that receives the first oscillation signal and a magnification selection signal and outputs a second oscillation signal, the period of the second oscillation signal is a period of the first oscillation signal or a period of an oscillation adjustment signal, and the second oscillation signal is selected according to the magnification selection signal; and a pulse conversion circuit that receives the second oscillation signal and outputs a pulse signal, the pulse of the pulse signal is generated according to the rising or falling edge of the second oscillation signal, and the pulse period of the pulse signal is the same as the oscillation period of the second oscillation signal.

A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

A phase correction circuit includes a plurality of signal paths configured to transmit multi-phase signals. The phase correction circuit further includes a loop circuit coupled to the plurality of signal paths, the loop circuit configured to correct phase skew among the multi-phase signals by averaging the phases of two signals which are obtained by synthesizing a signal of each of the signal paths with another signal of a signal path different from the corresponding signal path.