A method for operating an electrical switching device and an electrical switching device are disclosed. In order to ensure reliable operation of an electrical switching device having parallel switching paths allocated to a phase, which have lower switching capacity in comparison to conventional parallel switching paths, the zero current crossings in the phase are detected and at least one switching mechanism, operatively connected to the switching paths, is actuated so that all parallel switching paths allocated to the phase open within a window of time which is in the phase relative to the zero current crossings.

A method for operating an electrical switching device and an electrical switching device are disclosed. In order to ensure reliable operation of an electrical switching device having parallel switching paths allocated to a phase, which have lower switching capacity in comparison to conventional parallel switching paths, the zero current crossings in the phase are detected and at least one switching mechanism, operatively connected to the switching paths, is actuated so that all parallel switching paths allocated to the phase open within a window of time which is in the phase relative to the zero current crossings.

To improve a timing error detection accuracy in a semiconductor integrated circuit provided with storage devices operating in synchronization with a clock signal.

A delay part delays a data signal by two mutually-different delay times and outputs it as first and second delay signals. A holding part holds the first and second delay signals in synchronization with a timing signal for giving an instruction on a predetermined capture timing. A setup time detection part detects whether or not one of the first and second delay signals held within a setup-time detection period from a predetermined start timing to the predetermined capture timing has changed. A hold time detection part detects whether or not the other of the first and second delay signals held within a hold-time detection period from the predetermined capture timing to a predetermined end timing has changed.

To improve a timing error detection accuracy in a semiconductor integrated circuit provided with storage devices operating in synchronization with a clock signal.

A delay part delays a data signal by two mutually-different delay times and outputs it as first and second delay signals. A holding part holds the first and second delay signals in synchronization with a timing signal for giving an instruction on a predetermined capture timing. A setup time detection part detects whether or not one of the first and second delay signals held within a setup-time detection period from a predetermined start timing to the predetermined capture timing has changed. A hold time detection part detects whether or not the other of the first and second delay signals held within a hold-time detection period from the predetermined capture timing to a predetermined end timing has changed.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

A circuit component has a network address. The network address is determined from a voltage level applied to a single electrical contact of the circuit component. The circuit component is configured to select from among at least three unique network addresses based on the voltage level.

A timer circuit is provided comprising: a resistor; a programmable gain circuit coupled to amplify the reference level based upon a resistor and a selected gain; a detection circuit coupled to identify the amplified reference level based upon a resistor; a selection circuit configured to select the gain based at least in part upon the identified amplified reference level based upon a resistor; a comparator circuit configured to transition between providing a signal having a first value and providing a signal having a second value based at least in part upon comparisons of a reactive circuit element excitation level with the amplified reference level based upon a resistor and with a second reference level; and reactive circuit element excitation circuit configured to reverse excitation of the reactive circuit element in response to the comparator circuit transitioning between providing the signal having the first value and providing the signal having the second value.

A circuit includes a sensor configured to receive an input signal and to provide a sensor output signal in response to the received input signal. A plurality of mirror circuits are configured to receive the sensor output signal from the sensor and to generate mirror circuit output signals. The plurality of mirror circuits includes a first mirror circuit and at least a second mirror circuit. The first mirror circuit increases its respective mirror circuit output signal until its saturation value is reached. The second mirror circuit increases its respective mirror output signal if the sensor output signal is above a threshold value and until its saturation value is reached.