A control circuit, a chip and a control method are disclosed. The control circuit includes: an adjustment signal generation unit configured to detect an electrical signal reflecting a power supplied to a load under control of a current value of a reference signal, generate a feedback signal and output an adjustment signal based on both the feedback signal and the reference signal; and a control unit coupled to the adjustment signal generation unit and configured to control the switching circuit on and off based on the adjustment signal. With the generated adjustment signal that reflects a change in an adjustment metric indicated in the reference signal, the control circuit and the driving system can be adapted in real time to the specifications of any AC power standard. Moreover, much more granular adjustments can be made in the power supplied to the load.

Embodiments of the disclosure are drawn to apparatuses and methods for a multi-bit duty cycle monitor. A clock signal may be provided to a memory in order to synchronize one or more operations of the memory. The clock signal may have a duty cycle which is adjusted by a duty cycle adjustor of the memory. The duty cycle of the adjusted clock signal may be monitored by a multi-bit duty cycle monitor. The multi-bit duty cycle monitor may provide a multi-bit signal which indicates if the duty cycle of the adjusted clock signal is above or below a target duty cycle value (or if the duty cycle is outside tolerances around the target duty cycle). The multi-bit duty cycle monitor may provide the multi-bit signal while access operations of the memory are occurring.

Embodiments of the disclosure are drawn to apparatuses and methods for lookahead duty cycle adjustment of a clock signal. Clock signals may be provided to a semiconductor device, such as a memory device, to synchronize one or more operations. A duty cycle adjuster (DCA) of the device may adjust the clock signal(s) based on a duty code determined during an initialization of the device. While the device is in operation, a lookahead DCA (LA DCA) may test a number of different adjustments to the clock signal(s), the results of which may be determined by a duty cycle monitor (DCM). The results of the DCM may be used to select one of the tested adjustments, which may be used to update the duty code.

An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.

A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input signal and to generate a rising edge of an output signal of the delay circuit, wherein the output signal is a delayed version of the input signal. The delay circuit further includes a first P-substage having a sourcing current source, configured to receive the input signal and to generate a falling edge of the output signal, where the sinking current source and the sourcing current source are variable in response to respective ones of a plurality of bias voltages.

A method for increasing power supply voltage in an information handling system in a normal mode with a first peak voltage comprises, in response to receiving a request for a higher peak voltage, an embedded controller (EC) receiving information associated with the application including a request for power at a higher peak voltage, a housekeeping IC communicating a signal to a PWM IC to increase voltage supplied to the information handling system to the higher peak voltage, the PWM IC converting from the PSU to the higher peak voltage and starting a timer with a defined time period. If no additional requests for operating at the higher peak voltage are received before the time period expires, the PWM IC communicates a signal that power will stop being supplied at the higher peak voltage, and the information handling system returns to operating in the normal mode at the first peak voltage.

A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

The inventive concepts relate to methods for duty cycle correction of an input signal and circuits thereof. The method comprising following operations of generating, a plurality of intermediate delayed input signals, each delayed by at least a unit delay, through a delay line driven by the input signal, selecting from among the plurality of delayed input signals, through a first control signal, where the selection is based on number of unit delays in the input signal, generating at least an incremented duty signal and a decremented duty signal based on the selected delayed signals and the input signal, generating, a corrected duty cycle based on the selection of at least one of: the incremented duty cycle or decremented duty cycle by providing a second control signal. The inventive concepts offer low power consumption and low area for correction or adjustment of the duty cycle of the input signal with higher probability or guaranteed monotonicity.

An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

A calibration circuit includes: a differential input circuit, configured to receive first and second oscillation signals, the first and second oscillation signals having the same frequency and opposite phases, duty cycle of the first oscillation signal and duty cycle of the second oscillation signal being in a first preset range, and the differential input circuit being configured to output first and internal signals; a comparison unit, connected to an output end of the differential input circuit and configured to compare duty cycle of the first internal signal and/or duty cycle of the second internal signal; and a logical unit, connected to the comparison unit and the differential input circuit, and configured to control the differential input circuit according to an output result of the comparison unit, such that the duty cycle of the first internal signal and/or the duty cycle of the second internal signal reaches a second preset range.