A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

A hearable has an audio amplifier circuit coupled to a speaker as a load. The amplifier circuit has current source drive, which attenuates electromagnetically coupled noise of the speaker. In other instances, the amplifier circuit has a first amplifier mode and a second amplifier mode, wherein in the first amplifier mode the amplifier circuit becomes configured to drive the speaker as a voltage source, and in the second amplifier mode the amplifier circuit becomes configured to drive the speaker as a current source. Control logic varies the amplifier circuit between i) the first amplifier mode for larger amplitudes of the audio signal, and ii) the second amplifier mode for smaller amplitudes of the audio signal. Other aspects are also described and claimed.

A system and method for efficient on-chip monitoring of clock signals post-silicon. An electronic circuit includes a post-silicon and on-die signal monitor and a first signal generator that sends a first signal with a first signal period to the signal monitor. The signal monitor selects a first sampling signal with a first sampling period such that a ratio of the first sampling period to the first signal period is greater than one and is a non-integer. The signal monitor selects a reference voltage level for indicating when the first signal is asserted. When the first sampling period has elapsed, the signal monitor samples the first signal to generate a voltage level, and upon completing sampling, determines a duty cycle of the generated voltage levels, which indicates a duty cycle of the first signal. Using a similar approach, the signal monitor is also capable of determining skew between two signals.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters configured to output a first set of phase clock signals having a first duty cycle. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to a multiplexed selection signal, the first clock output signal having a second duty cycle; and adjust the second duty cycle responsive to at least a set of control signals or a phase difference between a first and second phase clock signal. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and to generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.

A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock by means of a voltage-controlled oscillator of the counting circuit according to the base clock and the comparator output signal, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate the counting output.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.

Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.

A duty cycle correction (DCC) circuit for use in relation to differential signal communications, a method of providing duty cycle correction, and communications systems and methods employing same, are disclosed herein. In one example embodiment, the circuit includes a differential signal inverter circuit including first and second inverter circuits, each of which has a respective inverter and respective first and second transistor devices respectively coupled between the respective inverter and first and second voltages, respectively. The circuit also includes a feedback circuit coupled to respective output ports of the respective first and second inverter circuits and also to respective feedback input ports of the respective transistor devices. The feedback circuit operates to provide one or more feedback signals causing one or more of the transistor devices to perform current limiting. Respective duty cycles of output signals respectively are equal or substantially equal based on the current limiting.

A method for increasing power supply voltage in an information handling system in a normal mode with a first peak voltage comprises, in response to receiving a request for a higher peak voltage, an embedded controller (EC) receiving information associated with the application including a request for power at a higher peak voltage, a housekeeping IC communicating a signal to a PWM IC to increase voltage supplied to the information handling system to the higher peak voltage, the PWM IC converting from the PSU to the higher peak voltage and starting a timer with a defined time period. If no additional requests for operating at the higher peak voltage are received before the time period expires, the PWM IC communicates a signal that power will stop being supplied at the higher peak voltage, and the information handling system returns to operating in the normal mode at the first peak voltage.