One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Routines and methods disclosed herein can increase a power efficiency of a prosthetic hand without drastically reducing the speed at which it operates. A prosthesis can implement an acceleration profile, which can reduce an energy consumption of a motor, or an amount of electrical and/or mechanical noise produced by a motor, as the motor as the motor transitions from an idle state to a non-idle state. A prosthesis can implement a deceleration profile, which can reduce the energy consumption of the motor, or an amount of electrical and/or mechanical noise produced by a motor, as the motor transitions from a non-idle state to an idle state.

Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

Power to an electrical device is controlled using a phase control that changes a cutoff phase of an alternating current (AC) electrical signal delivered to the electrical device. The power delivered to the electrical device is increased to an operational level using the phase control. A level of the power delivered to the electrical device is maintained at the operational level using an integral half cycle control that selectively removes a plurality of half cycles from the AC electrical signal delivered to the electrical device such that a plurality of remaining half cycles in the AC electrical signal delivered to the electrical device have a frequency outside a range of sub-harmonic frequencies.

Power to an electrical device is controlled using a phase control that changes a cutoff phase of an alternating current (AC) electrical signal delivered to the electrical device. The power delivered to the electrical device is increased to an operational level using the phase control. A level of the power delivered to the electrical device is maintained at the operational level using an integral half cycle control that selectively removes a plurality of half cycles from the AC electrical signal delivered to the electrical device such that a plurality of remaining half cycles in the AC electrical signal delivered to the electrical device have a frequency outside a range of sub-harmonic frequencies.

An embodiment method for modifying the frequency of a clock signal clocking an integrated circuit supplied by a voltage controller comprises, in response to a command for the modification, varying the frequency of the clock signal at a rate allowing a supply voltage to be controlled by the controller. The variation comprises at least one series of successive divisions of the frequency of the clock signal into successive intermediate signals of respective intermediate frequencies.

Examples describe a duty cycle correction circuit for correcting duty cycle distortion from memory. One example is an integrated circuit for correcting an input clock signal. The integrated circuit includes a first leg circuit and a second leg circuit. The first leg circuit and the second leg circuit both comprise a charging circuit and a discharging circuit. Each charging circuit comprises a first plurality of transistors and each discharging circuit comprises a second plurality of transistors. The charging circuit is coupled to the discharging circuit in series. A number of transistors of the first plurality of transistors in the first leg circuit is different from a number of transistors of the first plurality of transistors in the second leg circuit.

A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock by means of a voltage-controlled oscillator of the counting circuit according to the base clock and the comparator output signal, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate the counting output.

One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.