An apparatus comprising an encoder is configured to: detect a first edge in the input signal and, in response, provide a pulse generation sequence comprising the encoder being configured to: generate, in the output signal, a first pulse, wherein the first pulse is provided over first and second minimum time periods irrespective of an edge subsequent the first edge being present in the input signal; and obtain a first sample of the input signal; and obtain a second sample at an end of the first pulse; and if the first sample and the second sample are indicative of different voltage levels, generate a second pulse; or if the first and second sample and the same maintain the voltage level in the output signal.

A spike generation circuit includes a first CMOS inverter connected between a first power supply and a second power supply, an output node of the first CMOS inverter being coupled to a first node that is an intermediate node coupled to an input terminal to which an input signal is input, a switch connected in series with the first CMOS inverter, between the first power supply and the second power supply, a first inverting circuit that outputs an inversion signal of a signal of the first node to a control terminal of the switch, and a delay circuit that delays the signal of the first node, outputs a delayed signal to an input node of the first CMOS inverter, and outputs an isolated output spike signal to an output terminal.

A circuit includes a period calculator and a pulse width calculator. The period calculator is configured for receiving a first predetermined digital code and a second predetermined digital code, and for calculating a first calculated period value according to the first predetermined digital code, and calculating a second calculated period value according to the second predetermined digital code. The first predetermined digital code has a first predetermined period value, and the second predetermined digital code has a second predetermined period value. The pulse width calculator is configured for receiving a predetermined pulse width, and calculating a first pulse width code corresponding to the predetermined pulse width according to the first predetermined period value, the second predetermined period value, the first calculated period value, the second calculated period value and the predetermined pulse width.

The present invention relates to the technical field of printing in particular, to a frequency multiplication method and device, for solving the problem of poor quality of a printed image. One method comprises: for two adjacent pulse signals output from an encoder, determining a first kind of pulse signals and a second kind of pulse signals to be inserted between the two adjacent pulse signals according to a time interval between the two adjacent pulse signals and a frequency multiplication value corresponding to a longitudinal resolution; determining a period of the first kind of pulse signals to be inserted between the two adjacent pulse signals, and determining a period of the second kind of pulse signals to be inserted between the two adjacent pulse signals; and performing frequency multiplication processing on the two adjacent pulse signals. The embodiments of the invention further improve the printing quality of images.

The present invention relates to the technical field of printing in particular, to a frequency multiplication method and device, for solving the problem of poor quality of a printed image. One method comprises: for two adjacent pulse signals output from an encoder, determining a first kind of pulse signals and a second kind of pulse signals to be inserted between the two adjacent pulse signals according to a time interval between the two adjacent pulse signals and a frequency multiplication value corresponding to a longitudinal resolution; determining a period of the first kind of pulse signals to be inserted between the two adjacent pulse signals, and determining a period of the second kind of pulse signals to be inserted between the two adjacent pulse signals; and performing frequency multiplication processing on the two adjacent pulse signals. The embodiments of the invention further improve the printing quality of images.

Examples may include techniques for dual-range clock duty cycle tuning of a clock signal used for an input/output data bus. A clock duty cycle of the clock signal is monitored to determine whether the clock duty cycle falls within a threshold of a 50 percent duty cycle. A dual-range tuning is then implemented until the clock duty cycle of the clock signal falls within the threshold.

The embodiments of the present invention provide an apparatus of an efficient digital duty cycle adjuster and the method of operation thereof. The method includes: providing an input clock having an input clock duty cycle; inserting at least one programmable delay of a programmable delay line to the input clock, the input clock has a first delay inserted for a delayed rise edge, and a second delay inserted for a delayed fall edge, wherein the first delay, the second delay, or the combination thereof, includes the programmable delay; and adjusting an output clock duty cycle of an output clock by configuring the programmable delay, the output clock is generated by a selecting circuit, the selecting circuit includes a select signal, and the select signal is determined in accordance with the first delay and the second delay.

A circuit includes first and second transistors, a capacitor, and a controller. The controller is coupled to the control inputs of the first and second transistors. The controller configured to, during a first mode and in accordance with a first time-varying duty cycle, turn on and off the first transistor while turning on the second transistor when the first transistor is off. The controller is also configured to, during a second mode following the first mode, and in accordance with a second time-varying duty cycle, turn on and off the first transistor while turning on the second transistor when the first transistor is off.

A method and device for processing a signal (CRK) provided by a bidirectional sensor, the method includes the following steps: generation of a first signal (CRK_CNT) utilizing all the slots of the signal provided by the sensor, generation of a second signal (CRK_FW) utilizing the slots corresponding to a first direction of transit, generation of a third signal (CRK_BW) utilizing the slots corresponding to a second direction of transit, connection of the first signal to the input of the first electronic component, connection of the second and third signals to a second component, detection by the second component of edges of the signals received, change of the value of the predefined threshold (THMI) in the first component upon each detection of an edge.

A method and device for processing a signal (CRK) provided by a bidirectional sensor, the method includes the following steps: generation of a first signal (CRK_CNT) utilizing all the slots of the signal provided by the sensor, generation of a second signal (CRK_FW) utilizing the slots corresponding to a first direction of transit, generation of a third signal (CRK_BW) utilizing the slots corresponding to a second direction of transit, connection of the first signal to the input of the first electronic component, connection of the second and third signals to a second component, detection by the second component of edges of the signals received, change of the value of the predefined threshold (THMI) in the first component upon each detection of an edge.