A circuit system is disclosed. In one example, the circuit system includes a clock tree circuit with multiple lanes to which a clock signal is distributed. A duty correction circuit is provided for each of the multiple lanes, and corrects a duty ratio of the clock signal. A clock gating circuit group has a clock gating circuit for each of the multiple lanes and receives, as input, the clock signal from the duty correction circuit. The clock gating circuit group starts output of the clock signal from each of a plurality of the clock gating circuits in a predetermined period. A variable delay circuit is provided in association with each of a plurality of the duty correction circuits and is capable of changing a delay time of a control signal that controls a timing of starting output of the clock signal from the clock gating circuit.

A duty cycle correction (DCC) circuit for use in relation to differential signal communications, a method of providing duty cycle correction, and communications systems and methods employing same, are disclosed herein. In one example embodiment, the circuit includes a differential signal inverter circuit including first and second inverter circuits, each of which has a respective inverter and respective first and second transistor devices respectively coupled between the respective inverter and first and second voltages, respectively. The circuit also includes a feedback circuit coupled to respective output ports of the respective first and second inverter circuits and also to respective feedback input ports of the respective transistor devices. The feedback circuit operates to provide one or more feedback signals causing one or more of the transistor devices to perform current limiting. Respective duty cycles of output signals respectively are equal or substantially equal based on the current limiting.

Embodiments disclosed herein provide an apparatus comprising a clock generation circuit configured to generate a first signal for a first time period and a second signal for a second time period, a charge pump circuit coupled to the clock generation circuit and configured to generate a first voltage and a second voltage based, at least in part, on the first time period and the second time period, and a comparison circuit coupled to the charge pump circuit, the comparison circuit configured to compare a difference between the first voltage and the second voltage with a threshold value and generate an active tracking enablement signal in response to determining that the difference between the first and second voltages exceeds the threshold value.

A device for correcting a multi-phase clock signal includes a first duty ratio adjusting circuit (DRAC) to adjust a duty ratio of a first clock signal; a variable delay line (VDL) delaying a second clock signal; a second DRAC adjusting a duty ratio of the VDL output; first and second differential clock generating circuits (DFCGs) generating differential signals from first and second DRAC outputs, respectively; an edge combining circuit combining edges of outputs from the DFCGs; a duty ratio detecting circuit (DRDC) detecting a duty ratio of a first DRAC output or a first DFCG output in a first mode and of an edge combining circuit output in a second mode; a first control circuit controlling the first and second DRACs using a DRDC output in the first mode; and a second control circuit controlling the VDL using the DRDC output in the second mode.

Example embodiments of systems, methods, and computer-accessible mediums for identity verification and transaction authentication are provided. An exemplary system can comprise an application, a user device, and a server. The application can prompt a removal of a card chip, prompt an insertion of the card chip into the user device, determine an orientation of the card chip after the insertion of the card chip into the user device, and transmit, to the card chip, a first message. The card chip can encrypt the first message via one or more authentication protocols to generate an encrypted first message, transmit, to the server, the encrypted first message. The server can decrypt the encrypted first message, verify the decrypted first message, and transmit a second message to the application, wherein the application is configured to display a verification notification in response to the second message.

A duty adjustment circuit, and a delay locked loop circuit and a semiconductor memory device including the same are provided. The duty adjustment circuit includes a pulse generator configured to generate a pulse signal at a constant pulse width regardless of a frequency of a reference clock signal, based on frequency information, a code generator configured to generate a first predetermined number of delayed pulse signals by delaying the pulse signal, as a first code in response to the pulse signal, and a duty adjuster configured to receive a delay clock signal, and generate a duty correction clock signal by adjusting a slope of rising transition and a slope of falling transition of the delay clock signal in response to the first code and a second code.

There is provided an electronic circuit including a timing signal generation unit for generating a timing signal; a data signal supply unit for synchronizing with the timing signal generated to supply a data signal; a data signal transmission circuit for transmitting the data signal supplied; a timing signal transmission circuit for transmitting the timing signal generated by a circuit having a substantially same delay time as the data signal transmission circuit; and a data holding unit for synchronizing with the timing signal transmitted to hold and output the data signal transmitted. Also, there are provided a solid state image capturing apparatus and a method of controlling the electronic circuit.

A clock spread spectrum circuit, an electronic equipment, and a clock spread spectrum method are disclosed. The clock spread spectrum circuit includes a control circuit, a signal generation circuit, and a duty cycle adjustment circuit. The duty cycle adjustment circuit is configured to generate a target voltage having a duty cycle that is equal to a target duty cycle, the control circuit is configured to generate a frequency control word according to a modulation parameter, and the frequency control word changes discretely with time; and the signal generation circuit is configured to receive the target voltage and the frequency control word and generate and output a spread spectrum output signal that is spectrum-spread according to the target voltage and the frequency control word, and the spread spectrum output signal corresponds to the frequency control word and a duty cycle of the spread spectrum output signal is the target duty cycle.

A duty correction circuit may be provided. The duty correction circuit may include a control circuit configured to generate a duty correction control signal by detecting edges of first and second differential clock signals. The duty a duty correction clock signal generation circuit may be configured to generate a duty correction clock signal according to edges of the duty correction control signal.

Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.