A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

Techniques are provided for automatic gain control processing to reduce adverse effects associated with clipped samples resulting from conversion of analog signals to digital signals. A methodology according to an embodiment includes identifying a clipped sample of the digital signal, for example by comparison of the digitized sample values to a threshold value associated with a full scale value of the converter. The method also includes applying a window function to portions of the digital signal. The window function is configured to attenuate samples of the digital signal within a region centered on the identified clipped sample. A Hilbert finite impulse response (FIR) filter may be applied to the digital signal prior to applying the window function. Parameters of the window function are selected based on frequency response characteristics of the FIR filter and on signal to noise ratio requirements of an application that receives the windowed digital signal.

A voltage-controlled oscillator is provided. A semiconductor device includes a first circuit and a second circuit. The first circuit has a function of holding a first potential and a function of controlling the level of a third potential supplied to the second circuit according to a second potential based on the first potential. The second circuit has a function of outputting a second signal based on a first signal input to the second circuit. The delay time from input of the first signal to the second circuit to output of the second signal from the second circuit is determined by the third potential.

A voltage-controlled oscillator is provided. A semiconductor device includes a first circuit and a second circuit. The first circuit has a function of holding a first potential and a function of controlling the level of a third potential supplied to the second circuit according to a second potential based on the first potential. The second circuit has a function of outputting a second signal based on a first signal input to the second circuit. The delay time from input of the first signal to the second circuit to output of the second signal from the second circuit is determined by the third potential.

An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.

A data receiver includes a plurality of samplers, each of the samplers amplifies a difference between a first reference voltage and an input voltage and amplifies a difference between a second reference voltage and the input voltage. Operational paths of the samplers are differently controlled according to a level of second data corresponding to the second reference voltage, and first data corresponding to the first reference voltage is past data preceding current data and the second data is past data preceding the first data in the sampler.

The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.

The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.

A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal.

A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first delay circuit is coupled to the first terminal and the second terminal. The first delay circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and with a delay between successive ON times of the first switch and the second switch. The second delay circuit is coupled to the first terminal and the second terminal. The second delay circuit is configured to control the first delay circuit to generate the delay in accordance with a stored setting of the delay, a first voltage on the first terminal, or a second voltage on the second terminal.