An analog signal is accurately converted into a digital signal. An oscillator generates an oscillation signal having a cycle that depends on a signal level of an input analog signal. A current bit generation unit generates, as a current bit, a bit indicating a value of the oscillation signal at each of a plurality of timings within the cycle. A delay unit delays each current bit over a predetermined period and supplies the delayed current bit as a delayed bit. A determination unit determines whether a change amount of a phase of the oscillation signal changed within the predetermined period is greater than a half cycle of the cycle. An output unit generates and outputs data indicating a period in which respective values of the current bit and the delayed bit form a specific combination when the change amount is not greater than the half cycle, and generates and outputs data indicating a period in which the respective values of the current bit and the delayed bit are the same or form the specific combination when the change amount is greater than the half cycle.

An analog signal is accurately converted into a digital signal. An oscillator generates an oscillation signal having a cycle that depends on a signal level of an input analog signal. A current bit generation unit generates, as a current bit, a bit indicating a value of the oscillation signal at each of a plurality of timings within the cycle. A delay unit delays each current bit over a predetermined period and supplies the delayed current bit as a delayed bit. A determination unit determines whether a change amount of a phase of the oscillation signal changed within the predetermined period is greater than a half cycle of the cycle. An output unit generates and outputs data indicating a period in which respective values of the current bit and the delayed bit form a specific combination when the change amount is not greater than the half cycle, and generates and outputs data indicating a period in which the respective values of the current bit and the delayed bit are the same or form the specific combination when the change amount is greater than the half cycle.

A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

A logic two-to-one multiplexer includes: two input terminals; one output terminal; a control terminal. Four series-connected two-to-one multiplexers are connected such that a first multiplexer has its inputs connected to the input terminals, a last multiplexer has its output connected to the output terminal, and the other multiplexers have their respective inputs interconnected to the output of the previous multiplexer in the series association. Half of the multiplexers are controlled in reverse with respect to the other half of the multiplexers.

A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

An apparatus and associated methodology providing read channel circuitry having a signal equalizer that sends an equalized signal to a bit detector. The read channel circuitry is capable of sampling values of the equalized signal to identify a bit transition from among a predefined plurality of different bit transitions. The apparatus may have channel optimization (CO) logic that, based on the input signal and the sampling of the equalized signal, defines first values for a programmable parameter of the bit detector that substantially maximizes vector separations among vectors of waveform target samples corresponding to the predefined plurality of different bit transitions, while the CO logic also defines second values for a programmable parameter of the equalizer that substantially minimizes the mean squared separation of the equalized signal segment for each bit transition from the waveform target corresponding to that bit transition.

A pulse generator comprising: a first signal generating arm comprising a first inductor and a plurality of switching elements, each arranged to draw current through the first inductor; and a controller arranged to activate the plurality of switching elements in a predetermined sequence so as to generate a predetermined pulse waveform at a pulse generator output. The switching elements of the signal generating arm and the inductor together form a pulse synthesizer that takes the signal from the controller and uses it to synthesize an output pulse. Compared with conventional transmitter architectures, the functions of the upconversion mixer, the DAC, and the power amplifier are all performed by a single simplified circuit. This is both area efficient and power efficient.

A data processor includes at least one power supply voltage terminal for receiving a power supply voltage and a power supply current, a data processing circuit, a register, and a port controller. The data processing circuit is coupled to the at least one power supply voltage terminal and operates using the power supply voltage. The register stores a nominal value of the power supply voltage, an electrical design current (EDC) limit, and an EDC slope, wherein the EDC slope specifies a desired voltage-current relationship for an external voltage regulator when the power supply current exceeds the EDC limit. The port controller is coupled to the register and to an output port. The data processing circuit is operative to cause the port controller to output the nominal value of the power supply voltage, the EDC limit, and the EDC slope over the output port for use by the external voltage regulator.