A fully connected ring oscillator circuit includes a plurality of first ring oscillator loops, a plurality of second ring oscillator loops, a plurality of ring oscillators and a plurality of coupled ring oscillators. Each first ring oscillator loop extends along a first axis. Each second ring oscillator loop extends along a second axis that is transverse to the first axis and intersects each of the first ring oscillator loops. Each ring oscillator includes one of the first ring oscillator loops connected to one of the second ring oscillator loops. Each coupled ring oscillator includes two of the ring oscillators that are connected to each other through a programmable weighted coupling block.

A system for transmitting a value via a pulse-width-modulated signal, comprises a transmitter and a receiver. The transmitter is configured for detecting the value and for outputting a pulse-width-modulated signal having a pulse width which represents the value or a range around the value. The receiver is configured for deriving the value or the range from the pulse-width-modulated signal, by evaluating the pulse width. The transmitter is furthermore configured to read back the emitted pulse-width-modulated signal and to check whether the value or the range can be derived from the emitted pulse-width-modulated signal, and, if the value or the range cannot be derived, to output an error signal to the receiver.

A system for transmitting a value via a pulse-width-modulated signal, comprises a transmitter and a receiver. The transmitter is configured for detecting the value and for outputting a pulse-width-modulated signal having a pulse width which represents the value or a range around the value. The receiver is configured for deriving the value or the range from the pulse-width-modulated signal, by evaluating the pulse width. The transmitter is furthermore configured to read back the emitted pulse-width-modulated signal and to check whether the value or the range can be derived from the emitted pulse-width-modulated signal, and, if the value or the range cannot be derived, to output an error signal to the receiver.

An aggregation unit (15a) aggregates an input pulse train signal including a time-series pulse corresponding to a predetermined observation time into pulses for respective unit times. A calculation unit (15b) calculates a time shift amount of an autocorrelation function using the aggregated pulse train signal. A detection unit (15c) calculates an autocorrelation value and a threshold with respect to each of time shift amounts selected in ascending order from the calculated time shift amount and detects the time shift amount as a period of the aggregated pulse train signal when the autocorrelation value exceeds the threshold. A conversion unit (15d) converts the detected period to a period of the input pulse train signal using the unit time. An exclusion unit (15e) excludes the pulse train signal having the converted period from the input pulse train signal.

An aggregation unit (15a) aggregates an input pulse train signal including a time-series pulse corresponding to a predetermined observation time into pulses for respective unit times. A calculation unit (15b) calculates a time shift amount of an autocorrelation function using the aggregated pulse train signal. A detection unit (15c) calculates an autocorrelation value and a threshold with respect to each of time shift amounts selected in ascending order from the calculated time shift amount and detects the time shift amount as a period of the aggregated pulse train signal when the autocorrelation value exceeds the threshold. A conversion unit (15d) converts the detected period to a period of the input pulse train signal using the unit time. An exclusion unit (15e) excludes the pulse train signal having the converted period from the input pulse train signal.

A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180 phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

A low-power phase interpolator circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts; a phase rotator circuit that outputs phase-adjusted clock signals, each phase-adjusted clock signal having a phase that lies within a range bounded by phases of two of the intermediate clock signals; a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180 phase difference; and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is arranged to transfer charge from the first supply power node to the second supply power node during a first time interval and to transfer charge from the second supply power node to the first supply power node during a second time interval.