An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.

The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

The present disclosure presents a circuit, a method, and a system to drive a half-bridge switch using depletion (D) mode compound semiconductor (III-V) switching transistors for a DC-DC converter using at least one driver to drive the switches of the circuit. Also included is at least one charge pump electrically connected to a gate of the transistor, to maintain a voltage that holds the transistor in an off-state. The circuit includes AC coupling capacitors to level shift a voltage and realize fast transistor switching.

An electronic device includes a transmission interface, a driving circuit, a receiving circuit, a sampling circuit, a detecting circuit, a timing control circuit and a processing circuit. The transmission interface is for connecting to another electronic device via a connecting cable. The driving circuit outputs a backward signal via the transmission interface to the another electronic device. The receiving circuit receives a received signal including the backward signal and a forward signal from the transmission interface. The sampling circuit samples the received signal to obtain a plurality of sample results. The detecting circuit detects transitions of the sample results to obtain a plurality of detection results. The processing circuit generates a control signal according to the detection results, and adjusts a time point at which the driving circuit outputs the backward signal through the timing control circuit.

An electronic device includes a transmission interface, a driving circuit, a receiving circuit, a sampling circuit, a detecting circuit, a timing control circuit and a processing circuit. The transmission interface is for connecting to another electronic device via a connecting cable. The driving circuit outputs a backward signal via the transmission interface to the another electronic device. The receiving circuit receives a received signal including the backward signal and a forward signal from the transmission interface. The sampling circuit samples the received signal to obtain a plurality of sample results. The detecting circuit detects transitions of the sample results to obtain a plurality of detection results. The processing circuit generates a control signal according to the detection results, and adjusts a time point at which the driving circuit outputs the backward signal through the timing control circuit.

An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.

An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.

A timing prediction circuit and method which relate to the field of circuit technologies and may be used to predict a timing margin of a to-be-predicted digital circuit, which are used to resolve a problem that a large quantity of devices are used to predict a probability that a timing error occurs in a to-be-predicted digital circuit. The timing prediction circuit includes a combinational logic circuit, a delay circuit, a sampling circuit, and a control circuit, where the sampling circuit includes N samplers, and an input end of each sampler is separately connected to an output end of the combinational logic circuit using the delay circuit, and an output end of each sampler is connected to an input end of the control circuit, where N is an integer equal, and N≧2. The present invention can be used to predict a timing margin of a to-be-predicted digital circuit.

An aggregation unit (15a) aggregates an input pulse train signal including a time-series pulse corresponding to a predetermined observation time into pulses for respective unit times. A calculation unit (15b) calculates a time shift amount of an autocorrelation function using the aggregated pulse train signal. A detection unit (15c) calculates an autocorrelation value and a threshold with respect to each of time shift amounts selected in ascending order from the calculated time shift amount and detects the time shift amount as a period of the aggregated pulse train signal when the autocorrelation value exceeds the threshold. A conversion unit (15d) converts the detected period to a period of the input pulse train signal using the unit time. An exclusion unit (15e) excludes the pulse train signal having the converted period from the input pulse train signal.

Implementations of conductive energy weapons (CEWs) may include a shock generating circuit configured to couple to a power source, two electrodes operatively coupled to the shock generating circuit, and a safety circuit operatively coupled to the shock generating circuit. The shock generating circuit may be configured to generate a first pulse train and deliver the first pulse train to a target, and may be configured to generate at least a second pulse train and deliver the at least second pulse train to a target. The safety circuit may be configured to prevent the CEW from applying pulse trains to the target after a predetermined number of pulse trains. The first pulse train may include two or more pulses having waveforms substantially identical with each other, each of the waveforms of the two or more pulses having both a positive voltage segment and a negative voltage segment.