A system and method for protecting against a voltage glitch are provided. Generally, the system includes a reset-detector coupled to a supply voltage (VCC) and to a power-on-reset (POR) block, and a glitch-detector coupled to VCC and the reset-detector. The reset-detector is operable to provide a signal to the POR block to generate a global-reset-signal when VCC decreases below a minimum and remains low for at least a first time. The glitch-detector is operable to provide a glitch-signal to the reset-detector to cause it to provide the signal to the POR block when VCC decreases below the minimum and remains low for at least a second time, where the second time is less than the first. The reset-detector can further include a retention-circuit operable to recall a glitch-signal was received and signal the POR block when VCC is restored. Other embodiments are also disclosed.

A multi-stream cross correlator for spiking neural networks, where each stream contains significant stochastic content. At least one event occurs, with a fixed temporal relationship across at least two streams. Each stream is treated as a Frame Of Reference (FOR), and subject to an adjustable delay based on comparison to the Other streams. For each spike of the FOR, a timing analysis, relative to the last and current FOR spikes, is completed by comparing Post and Pre accumulators. Also, a new timing analysis is begun, with the current FOR spike, by restarting the production of Post and Pre weighting functions, the values of which are accumulated, upon the occurrence of each Other spike, until a next FOR spike. A one-spike delay unit can be used, if time-neutral conflict resolution is used. The average spike rate of the FOR can be determined and used for the Post and Pre weighting functions.

A clock monitor circuit includes a monitor and a tunable counter. The monitor can monitor a clock under test. The tunable counter can count an integer according to a reference clock and set a target number. If a stable signal relative to the clock under test is toggled, the tunable counter can switch the target number from a large number to a small number. The tunable counter can perform an automatic detection process, so as to transmit a check signal to the monitor. In response to the check signal, if the clock under test is undetectable, the monitor will not transmit any confirmation signal back to the tunable counter, and the tunable counter will gradually increase the integer. When the integer is equal to the target number, the tunable counter generates a failure signal.

A clock monitor circuit includes a monitor and a tunable counter. The monitor can monitor a clock under test. The tunable counter can count an integer according to a reference clock and set a target number. If a stable signal relative to the clock under test is toggled, the tunable counter can switch the target number from a large number to a small number. The tunable counter can perform an automatic detection process, so as to transmit a check signal to the monitor. In response to the check signal, if the clock under test is undetectable, the monitor will not transmit any confirmation signal back to the tunable counter, and the tunable counter will gradually increase the integer. When the integer is equal to the target number, the tunable counter generates a failure signal.

An event detection controller for a circuit system controlled by a pulse wave modulation signal, can perform a specific event handling when a specific event is detected, wherein the specific event handling includes stopping a pulse wave modulation device, starting up the stopped pulse wave modulation device, controlling the pulse wave modulation device to change the pulse wave modulation signal, outputting a wake-up signal to wake up the circuit system, controlling the pulse detector to change its detection configuration, changing a cumulative occurrences number of the specific pattern of an event discrimination module, outputting a control signal or a first data signal to a peripheral device through a bus connected to an event response module and/or requesting the peripheral device to send a second data signal through the bus.

A fully connected ring oscillator circuit includes a plurality of first ring oscillator loops, a plurality of second ring oscillator loops, a plurality of ring oscillators and a plurality of coupled ring oscillators. Each first ring oscillator loop extends along a first axis. Each second ring oscillator loop extends along a second axis that is transverse to the first axis and intersects each of the first ring oscillator loops. Each ring oscillator includes one of the first ring oscillator loops connected to one of the second ring oscillator loops. Each coupled ring oscillator includes two of the ring oscillators that are connected to each other through a programmable weighted coupling block.

A method for preparing photoactive perovskite materials. The method comprises the steps of preparing a bismuth halide precursor ink. Preparing a bismuth halide precursor ink comprises the steps of introducing a bismuth halide into a vessel; introducing a first solvent to the vessel; and contacting the bismuth halide with the first solvent to dissolve the bismuth halide to form the bismuth halide precursor ink; depositing the bismuth halide precursor ink onto a substrate; drying the bismuth halide precursor ink to form a thin film; annealing the thin film; and rinsing the thin film with a solvent comprising: a second solvent; a first salt selected from the group consisting of methylammonium halide, formamidinimum halide, guanidinium halide, 1,2,2-triaminovinylammonium halide, and 5-aminovaleric acid hydrohalide; and a second salt selected from the group consisting of methylammonium halide, formamidinimum halide, guanidinium halide, 1,2,2-triaminovinylammonium halide, and 5-aminovaleric acid hydrohalide.

A method for preparing photoactive perovskite materials. The method comprises the steps of preparing a bismuth halide precursor ink. Preparing a bismuth halide precursor ink comprises the steps of introducing a bismuth halide into a vessel; introducing a first solvent to the vessel; and contacting the bismuth halide with the first solvent to dissolve the bismuth halide to form the bismuth halide precursor ink; depositing the bismuth halide precursor ink onto a substrate; drying the bismuth halide precursor ink to form a thin film; annealing the thin film; and rinsing the thin film with a solvent comprising: a second solvent; a first salt selected from the group consisting of methylammonium halide, formamidinimum halide, guanidinium halide, 1,2,2-triaminovinylammonium halide, and 5-aminovaleric acid hydrohalide; and a second salt selected from the group consisting of methylammonium halide, formamidinimum halide, guanidinium halide, 1,2,2-triaminovinylammonium halide, and 5-aminovaleric acid hydrohalide.

The disclosure discloses a wafer acceptance test module for a static memory function test, reduced instruction built-in self-test circuit formed on a wafer includes: a ring oscillator, a frequency divider, a counter, a data latch and comparator. The counter is used for count, and the count is used as an input signal of each of an address decoder and a data input port at the same time. The data latch and comparator is connected to an output terminal of the address decoder and an output terminal of the sense amplifier and compare two output signals to obtain a test result. The disclosure also discloses a wafer acceptance test method for a static memory function test. The disclosure does not need to rely on a dedicated test machine for memory to perform a static memory function test, which can simplify a test procedure.

Provided are a data signal detection device, and mobile industry processor interface radio frequency front-end device and system. The device includes: a first acquisition circuit, a second acquisition circuit and a selection output circuit. A first input terminal of the first acquisition circuit is connected to a second input terminal of the second acquisition circuit, and a second input terminal of the first acquisition circuit is connected to a first input terminal of the second acquisition circuit. Output terminals of the first acquisition circuit and the second acquisition circuit are connected to two input terminals of the selection output circuit. The acquisition circuit is configured to verify whether an acquisition signal meets a characteristic of a data signal; and the selection output circuit selects an acquisition signal from a received acquisition signal and a received invalid signal for output.