An integrated circuit includes a pipeline of compare logic stages. The pipeline, at successive pipeline stages, determines whether each of a set of input symbols meets a corresponding programmable criteria. The compare logic stages each compare the set of input symbols to a respective programmable value. The compare logic stages also each provide, to a respective successive compare logic stage, a corresponding plurality of indicators of whether respective ones of the set of input symbols met the corresponding programmable criteria for that compare logic stage. The corresponding programmable criteria are configurable to be based at least in part on the corresponding plurality of indicators from a respective previous compare logic stage.

An integrated circuit includes a pipeline of compare logic stages. The pipeline, at successive pipeline stages, determines whether each of a set of input symbols meets a corresponding programmable criteria. The compare logic stages each compare the set of input symbols to a respective programmable value. The compare logic stages also each provide, to a respective successive compare logic stage, a corresponding plurality of indicators of whether respective ones of the set of input symbols met the corresponding programmable criteria for that compare logic stage. The corresponding programmable criteria are configurable to be based at least in part on the corresponding plurality of indicators from a respective previous compare logic stage.

The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.

The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.

A system includes control circuitry configured to control an output signal. The control circuitry and/or various other sources of undesirable signal components may corrupt the control signal used by the control circuitry to correct the output signal. Conditioning circuitry may effect current-domain repair on the control circuitry by providing feedback-based conditioning actuation, including comparator overdrive, to the control circuitry.

A system includes control circuitry configured to control an output signal. The control circuitry and/or various other sources of undesirable signal components may corrupt the control signal used by the control circuitry to correct the output signal. Conditioning circuitry may effect current-domain repair on the control circuitry by providing feedback-based conditioning actuation, including comparator overdrive, to the control circuitry.

The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.

The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.

Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.