The physically unclonable function device (DIS) comprises a set of MOS transistors (TR1i, TR2j) mounted in diodes having a random distribution of respective threshold voltages, and comprising N first transistors and at least one second transistor. At least one output node of the function is capable of delivering a signal, the level of which depends on the comparison between a current obtained using a current circulating in the at least one second transistor and a current obtained using a reference current that is equal or substantially equal to the average of the currents circulating in the N first transistors. A first means (FM1i) is configured to impose on each first transistor a respective fixed gate voltage regardless of the value of the current circulating in the first transistor, and a second means (SM2j) is configured to impose a respective fixed gate voltage on each second transistor regardless of the value of the current circulating in the second transistor.

One example discloses a differential-signal-detection circuit, including: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal; a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal; wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

One example discloses a differential-signal-detection circuit, including: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive both the first differential output signal and the second differential output signal, and in response generate a first comparator output signal; a second comparator coupled to receive both the first differential output signal and the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal; wherein the output stage includes a deglitch circuit configured to attenuate changes in the differential-signal-detection signal during an inter-symbol period of the differential input signal.

An apparatus includes a comparator. The comparator includes a plurality of pregain stages, and a switch network coupled to the plurality of pregain stages. The comparator further includes a latch coupled to the plurality of pregain stages.

The semiconductor device comprises a first ring oscillator and a second ring oscillator. An input of the first ring oscillator is an end output of the first ring oscillator and an output of the second ring oscillator and wherein an input of the second ring oscillator is an end output of the second ring oscillator and an output of the first ring oscillator.

The semiconductor device comprises a first ring oscillator and a second ring oscillator. An input of the first ring oscillator is an end output of the first ring oscillator and an output of the second ring oscillator and wherein an input of the second ring oscillator is an end output of the second ring oscillator and an output of the first ring oscillator.

A current flow control device includes a plurality of semiconductor switches disposed between a power source and a load and that are connected in parallel with each other, and the current flow control device being configured to control the flow of current between the power source and the load by turning on and off the semiconductor switches. The plurality of semiconductor switches include a first and a second semiconductor switch. The current flow control device includes a driving circuit configured to apply, to the first semiconductor switch, a voltage that is higher than a voltage output from the power source, to turn on the first semiconductor switch, a switch control unit configured to turn on the second semiconductor switch, and a resistor that is connected in series with a terminal on the power source side of the second semiconductor switch, the resistor lowering a voltage applied to the terminal.

A high-resolution adaptive digital frequency synthesizer Integrated Circuit (IC) for wireless power systems, which comprises a digitally controlled tunable ring-oscillator, based on a chain of delay-line cells (DLs) being adapted to generate an internal high-resolution reference clock signal; a tuner unit for receiving as input a compensation/target signal and performing arithmetic operations that produce auxiliary tuning signals provided to the ring-oscillator, for allowing the ring-oscillator to generate a high-resolution output period/frequency; a counter-comparator unit introducing an additional delay to the chain, the counter-comparator unit operating in combination with the ring-oscillator and counts how many times the delay of the chain repeats, for providing ultra-fine tuning signal for tuning the frequency resolution of digitally controlled ring-oscillator; an adaptive Fractional-N dithering module, for enhancing the frequency resolution of the digitally controlled ring-oscillator by averaging the resolution provided by a single delay-line cell of the ring-oscillator.

A high-resolution adaptive digital frequency synthesizer Integrated Circuit (IC) for wireless power systems, which comprises a digitally controlled tunable ring-oscillator, based on a chain of delay-line cells (DLs) being adapted to generate an internal high-resolution reference clock signal; a tuner unit for receiving as input a compensation/target signal and performing arithmetic operations that produce auxiliary tuning signals provided to the ring-oscillator, for allowing the ring-oscillator to generate a high-resolution output period/frequency; a counter-comparator unit introducing an additional delay to the chain, the counter-comparator unit operating in combination with the ring-oscillator and counts how many times the delay of the chain repeats, for providing ultra-fine tuning signal for tuning the frequency resolution of digitally controlled ring-oscillator; an adaptive Fractional-N dithering module, for enhancing the frequency resolution of the digitally controlled ring-oscillator by averaging the resolution provided by a single delay-line cell of the ring-oscillator.

A modular power supply system is configured to include: a main controller, configured to output a main control signal; N local controllers, wherein each of the local controllers is configured to receive the main control signal to output at least one local control signal; N auxiliary power supplies, in one-to-one correspondence with the N local controllers, wherein each of the auxiliary power supplies is configured to provide power to the corresponding local controller, and N power units, in one-to-one correspondence with the N local controllers, wherein each of the power units includes a first end and a second end, the second end of each of the power units is connected to the first end of an adjacent one of the power units, each of the power units is configured to include M power converters, each of the power converters is configured to operate according to the local control signal.