A digital pulse width modulation driver system and method can include: receiving input digital data with a digital signal processing chip on a device; converting the input digital data into pulse width modulated data; generating an amplitude signal with the digital signal processing chip; transmitting the amplitude signal and the pulse width modulated data from a transmit interface within the device to a receive interface within an analog driver chip; and amplifying the pulse width modulated data with a driver coupled to a high voltage rail based on the amplitude signal corresponding to the high voltage rail, or amplifying the pulse width modulated data with the driver coupled to a low voltage rail based on the amplitude signal corresponding to the low voltage rail.

A transmission apparatus includes a waveform processing circuit. The waveform processing circuit is configured to receive a modulated signal indicating each of values of pulses by one of four signal levels including first, second, third, and fourth signal levels ascending in this order. The waveform processing circuit is configured to output a signal corresponding to the modulated signal. A portion of the output signal corresponding to a portion of the modulated signal that transitions between the first and fourth signal levels, transitions between a first adjusted signal level different from the first signal level and a second adjusted signal level different from the fourth signal level. The transmission apparatus is configured to transmit a signal corresponding to the signal output from the waveform processing circuit through a wired communication path.

The first stage of the differential interface circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gates of the first transistor and the second transistor are coupled to input terminals, respectively. The third transistor and the fourth transistor are coupled in parallel with the first transistor and the second transistor, respectively. The gate of the third transistor is coupled to the drain of the second transistor, and the gate of the fourth transistor is coupled to the drain of the first transistor.

The first stage of the differential interface circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The gates of the first transistor and the second transistor are coupled to input terminals, respectively. The third transistor and the fourth transistor are coupled in parallel with the first transistor and the second transistor, respectively. The gate of the third transistor is coupled to the drain of the second transistor, and the gate of the fourth transistor is coupled to the drain of the first transistor.

A hybrid voltage mode (VM) and current mode (CM) four-level pulse amplitude modulation (PAM-4) transmitter circuits (a.k.a. drivers) is calibrated using a configurable replica circuit and calibration control circuitry. The replica circuit includes an on-chip termination impedance to mimic a receiver's termination impedance. The amount of level enhancement provided by the current mode circuitry is calibrated by adjusting the current provided to the output node and sunk from the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving an intermediate PAM-4 level. After the level enhancement has been set, the non-linearity between levels is calibrated by adjusting the amount of current provided to the output node by the replica current mode circuitry while the replica voltage mode circuitry is driving a maximum output voltage level.

The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

Methods, systems, and devices for techniques for communicating multi-level signals are described. A first device may be configured to communicate signals with a second device according to a modulation scheme. The first device may transmit a first signal to the second device at a first voltage level of the modulation scheme corresponding to a first multi-bit value. The first device may select a second voltage level of the modulation scheme based on a difference between the first voltage level and a third voltage level of the PAM scheme, and may transmit a second signal to the second device at the second voltage level to indicate a second multi-bit value corresponding to the third voltage level. The second device may decode the second signal to determine the second multi-bit value based on receiving the first signal at the first voltage level and the second signal at the second voltage level.

Methods, systems, and devices for techniques for communicating multi-level signals are described. A first device may be configured to communicate signals with a second device according to a modulation scheme. The first device may transmit a first signal to the second device at a first voltage level of the modulation scheme corresponding to a first multi-bit value. The first device may select a second voltage level of the modulation scheme based on a difference between the first voltage level and a third voltage level of the PAM scheme, and may transmit a second signal to the second device at the second voltage level to indicate a second multi-bit value corresponding to the third voltage level. The second device may decode the second signal to determine the second multi-bit value based on receiving the first signal at the first voltage level and the second signal at the second voltage level.

Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.

Devices and methods are described herein for a pulse amplitude modulation (PAM) driver. In one embodiment, the PAM driver includes a first high-speed buffer configured to output a first voltage, a second high-speed buffer configured to output a second voltage, and a plurality of transistors coupled to the first high-speed buffer and the second high-speed buffer. At least one of the first voltage or the second voltage facilitates selective operation of a transistor of the plurality of transistors to output a third voltage.