A circuit includes a first and a second solid state electronic device arranged in a bridge-leg configuration, each selectively operable as a control switch and synchronous switch and each selectively operable in an ON state and OFF state. A driver circuit is operably connected with at least the first solid state electronic device for controlling operation of at least the first solid state electronic device. A signal modulation circuit is operably connected with or between the driver circuit and the first solid state electronic device and includes an input operably connected with the driver circuit, an output operably connected with the first solid state electronic device, and a variable resistance circuit operably connected between the input and the output and operably connected with the driver circuit. A resistance of the variable resistance circuit is adjustable by the driver circuit to prevent spurious operation of the first solid state electronic device.

A circuit includes a first and a second solid state electronic device arranged in a bridge-leg configuration, each selectively operable as a control switch and synchronous switch and each selectively operable in an ON state and OFF state. A driver circuit is operably connected with at least the first solid state electronic device for controlling operation of at least the first solid state electronic device. A signal modulation circuit is operably connected with or between the driver circuit and the first solid state electronic device and includes an input operably connected with the driver circuit, an output operably connected with the first solid state electronic device, and a variable resistance circuit operably connected between the input and the output and operably connected with the driver circuit. A resistance of the variable resistance circuit is adjustable by the driver circuit to prevent spurious operation of the first solid state electronic device.

The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

The present technology relates to a modulator and a modulation method for enabling provision of a highly convenient modulator. The modulator is configured to be input a first signal corresponding to one of a positive signal and a negative signal constituting a baseband signal of a differential signal, and a second signal having the same level as the first signal in one of an H level section in which the one signal is at an H level and an L level section in which the one signal is at an L level, and configured to generate a modulation signal obtained by modulating a carrier with the first and second signals to generate a modulation signal that is the amplitude shift keying (ASK)-modulated carrier with the baseband signal. The present technology can be applied to a case of modulating a carrier according to a baseband signal, for example.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

A method includes: sending, by a signal transmitting device, a first PAM signal to a signal receiving device, where the first PAM signal includes N first level amplitudes, and N3; receiving, by the transmitting device, feedback parameters sent by the receiving device, where the feedback parameters are determined based on the first PAM signal; determining, by the transmitting device, N target level amplitudes based on the feedback parameters, where intervals between every two adjacent target level amplitudes in the N target level amplitudes are different from each other; and generating, by the transmitting device based on the N target level amplitudes, a second PAM signal that needs to be sent to the receiving device.

A ternary pulse width modulation (PWM) method and apparatus. In one embodiment, the start of the pulse sequence in the current frame is referenced to the end of the pulse sequence in a previous, reference frame, rather than to the frame boundary at the start of the current frame, thereby allowing the compensation portion of the pulse sequence to overlap into the preceding or following frame, thus achieving a higher modulation index without dropping the compensation pulses. Although in most instantiations, the reference frame will be the frame immediately preceding in time the current frame, in other instances, the reference frame may be any frame preceding the current frame that falls within the constraints of the timing facility.

A ternary pulse width modulation (PWM) method and apparatus. In one embodiment, the start of the pulse sequence in the current frame is referenced to the end of the pulse sequence in a previous, reference frame, rather than to the frame boundary at the start of the current frame, thereby allowing the compensation portion of the pulse sequence to overlap into the preceding or following frame, thus achieving a higher modulation index without dropping the compensation pulses. Although in most instantiations, the reference frame will be the frame immediately preceding in time the current frame, in other instances, the reference frame may be any frame preceding the current frame that falls within the constraints of the timing facility.