Patent classifications
H03K7/02
Unequally spaced pulse amplitude modulation scheme
A digital communication technique, implementable in a digital communication system, includes performing a training phase in which the transmitter sends one or more transmissions of pulse amplitude modulation (PAM) signals wherein the PAM signals are modulated using one or more data-to-PAM-symbol mapping schemes, performing a feedback phase in which the transmitter receives a feedback message from a receiver, the feedback message indicative of a change to be made to data-to-PAM-symbol modulation schemes, and implementing a data transmission phase in which data is transmitted using a current PAM symbol mapping scheme based on the feedback message, wherein at least some symbols of the current PAM symbol modulation scheme are unequally spaced with respect to each other.
PULSE AMPLITUDE MODULATION TRANSMITTER AND PULSE AMPLITUDE MODULATION RECEIVER
A transmitter includes: a pulse amplitude modulation encoder that encodes serial data to multi-bit transmission data of a first data group and a second data group; a first driver that converts first multi-bit transmission data of the first data group to a first differential signal having a first voltage swing width; a second driver that converts second multi-bit transmission data of the second data group to a second differential signal having a second voltage swing width narrower than the first voltage swing width; a first voltage regulator that provides to the second driver a first low swing voltage for generating the second differential signal; a second voltage regulator that provides to the second driver a second low swing voltage less than the first low swing voltage; and a constant current load switch that provides a current path between the first and second voltage regulators depending on deactivation of the second driver.
Pulse-amplitude modulated hybrid comparator circuit
Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal.
Pulse-amplitude modulated hybrid comparator circuit
Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input signal with a reference signal to provide a first output signal at an output node of the first latch, and a second latch coupled to the output node of the first latch, the second latch including a complementary metal-oxide semiconductor (CMOS) inverter to generate a second output signal at an output node of the second latch based on the first output signal. The second output signal has a signal swing greater than a signal swing of the first output signal.
Low-power decision threshold control for high-speed signaling
An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.
Low-power decision threshold control for high-speed signaling
An apparatus and method and system therefor relates generally to decision threshold control. In such an apparatus, an ac-coupler circuit is configured as a high-pass circuit path for a first frequency range. A buffer amplifier circuit is coupled in parallel with the ac-coupler circuit. The buffer amplifier circuit is configured as a low-pass circuit path for a second frequency range. An offset injection circuit is coupled to both the ac-coupler circuit and the buffer amplifier circuit and configured to inject an offset.
UNEQUALLY SPACED PULSE AMPLITUDE MODULATION SCHEME
A digital communication technique, implementable in a digital communication system, includes performing a training phase in which the transmitter sends one or more transmissions of pulse amplitude modulation (PAM) signals wherein the PAM signals are modulated using one or more data-to-PAM-symbol mapping schemes, performing a feedback phase in which the transmitter receives a feedback message from a receiver, the feedback message indicative of a change to be made to data-to-PAM-symbol modulation schemes, and implementing a data transmission phase in which data is transmitted using a current PAM symbol mapping scheme based on the feedback message, wherein at least some symbols of the current PAM symbol modulation scheme are unequally spaced with respect to each other.
Amplitude adjustment circuit, digital coherent receiver, and amplitude adjustment method
An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.
Amplitude adjustment circuit, digital coherent receiver, and amplitude adjustment method
An amplitude adjustment circuit includes a memory that stores correspondence information between frequency distributions of an amplitude and adjustment coefficients, a processor configured to generate a frequency distribution of amplitude of data for which adaptive equalization processing has been executed, acquire the correspondence information between frequency distributions of the amplitude and adjustment coefficients from the memory, select the adjustment coefficient based on a result of comparison between the frequency distributions included in the correspondence information acquired by the acquiring unit and the frequency distribution generated by the generating unit, and adjust a gain of the data based on the adjustment coefficient selected by the selecting unit.
PAM4 signal generation apparatus
A PAM4 signal generation apparatus is provided. The PAM4 signal generation apparatus includes a DFB, two EA modulators, an SOA, a PSR, a direct-current power source, two electrical-signal generators, and two amplitude-limiting amplifiers. The two electrical-signal generators and the two amplitude-limiting amplifiers are used to generate two NRZ electrical signals respectively, the DFB outputs two optical signals, the SOA amplifies an optical power of one of the optical signals, the two EA modulators use the NRZ electrical signals and the optical signals including a large signal and a small signal respectively to generate two NRZ optical signals respectively, and the two NRZ optical signals are multiplexed by the PSR to generate a PAM4 electrical signal. According to this apparatus, a linearity requirement is greatly lowered. PAM4 modulation is performed in an optical domain, and this prevents a PAM4 signal from being generated on an electrical signal.