Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

A driver circuit for driving a passive resonant antenna-circuit, the latter comprising an inductance (L) and a capacitance (C) in parallel. The driver circuit comprises a first and a second interface node (Ni1, Ni2) connectable to the resonant antenna circuit, and comprises control circuitry for monitoring an oscillating voltage signal (Vosc) provided by the resonant antenna circuit, and for extracting timing information and amplitude information of said oscillating voltage signal (Vosc), and excitation circuitry for generating an excitation signal based on the measured timing and amplitude information, and for applying the excitation signal to the antenna circuit.

A method of operating a memory device includes receiving a training request for a data channel, detecting at least one mode parameter according to the training request, transmitting the detected mode parameter to an external device, setting at least one of an NRZ mode and a PAM4 mode to a transmission signaling mode based on mode register set setting information from the external device, and performing communications with the external device according to the set transmission signaling mode.

Methods, systems, and devices for techniques for communicating multi-level signals are described. A first device may be configured to communicate signals with a second device according to a modulation scheme. The first device may transmit a first signal to the second device at a first voltage level of the modulation scheme corresponding to a first multi-bit value. The first device may select a second voltage level of the modulation scheme based on a difference between the first voltage level and a third voltage level of the PAM scheme, and may transmit a second signal to the second device at the second voltage level to indicate a second multi-bit value corresponding to the third voltage level. The second device may decode the second signal to determine the second multi-bit value based on receiving the first signal at the first voltage level and the second signal at the second voltage level.

Methods, systems, and devices for techniques for communicating multi-level signals are described. A first device may be configured to communicate signals with a second device according to a modulation scheme. The first device may transmit a first signal to the second device at a first voltage level of the modulation scheme corresponding to a first multi-bit value. The first device may select a second voltage level of the modulation scheme based on a difference between the first voltage level and a third voltage level of the PAM scheme, and may transmit a second signal to the second device at the second voltage level to indicate a second multi-bit value corresponding to the third voltage level. The second device may decode the second signal to determine the second multi-bit value based on receiving the first signal at the first voltage level and the second signal at the second voltage level.

A communication device includes an AFE configured to track and hold a first driving signal to produce a plurality of sample signals, a shift and hold module configured to store the plurality of sample signals, and an ADC configured to respectively convert the plurality of sample signals to a plurality of digitized sample signals, the ADC including a plurality of ADC slices. A DSP is configured to calibrate the AFE based on the plurality of ADC slices corresponding to the plurality of digitized sample signals and generate an output data stream comprising the plurality of digitized samples. A skew management module is configured to detect a skew of the plurality of digitized sample signals in the output data stream generated by the DSP module, generate a programmable skew offset based on the detected skew, and correct the skew in the output data stream based on the programmable skew offset.

A converter includes: a terminal that receives code-modulated power into which first alternating-current power has been code-modulated with a modulation code; and a circuit that converts the code-modulated power with a conversion code to generate second alternating-current power. The conversion code is based on the modulation code. A frequency of the second alternating-current power is lower than a frequency of the first alternating-current power.

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second IO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.