A low power PAM-4 output transmitter is disclosed. The lower power PAM-4 output transmitter comprises a first source series terminated SST branch configured to include unit cells having transistors which are selectively activated in response to an input signal outputted from an encoder; a second SST branch configured to include unit cells having transistors which are selectively activated in response to a negative signal of the input signal; and a common voltage switch H3 configured to short or open the first SST branch and the second SST branch. Here, differential signals are outputted from both terminals of the first SST branch and the second SST branch by making the first SST branch and the second SST branch short or open according to an operation of the common voltage switch.

Embodiments herein relate to a transmitter which can operate in a non-return-to-zero (NRZ) mode or a pulse amplitude modulation (PAM) mode with three or more levels. The transmitter includes a first driver which processes most significant bits and a second driver which processes least significant bits, in the PAM3 mode. In the NRZ mode, the second driver is turned off but resistances in the second driver are used to optimize impedance in the first driver. Switches can be turned on to couple in resistors in the first driver with resistors in the second driver, for pairs of driver slices. The switches are turned off in the PAM3 mode.

Embodiments herein relate to a transmitter which can operate in a non-return-to-zero (NRZ) mode or a pulse amplitude modulation (PAM) mode with three or more levels. The transmitter includes a first driver which processes most significant bits and a second driver which processes least significant bits, in the PAM3 mode. In the NRZ mode, the second driver is turned off but resistances in the second driver are used to optimize impedance in the first driver. Switches can be turned on to couple in resistors in the first driver with resistors in the second driver, for pairs of driver slices. The switches are turned off in the PAM3 mode.

The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

Implementations of the present disclosure relate to a system comprising an access point (AP) and a USB device operating at the same frequency as the AP. The USB device may modulate a plurality of time-sensitive signals into a current pulse amplitude modulation (PAM) signal, and a plurality of different amplitudes in the current PAM signal is associated with occurrence of high level of a plurality of different combinations of time-sensitive signals in the plurality of time-sensitive signals. That is to say, when high level occurs in different numbers of time-sensitive signals, the modulated current PAM signal will have different power levels. Accordingly, the AP comprises a decoder for demodulating the current PAM signal to obtain a digital signal representing one or more time-sensitive signals transmitted from the USB device to the AP, thereby enabling the transmission of multiple time-sensitive signals from the USB device to the AP.

Implementations of the present disclosure relate to a system comprising an access point (AP) and a USB device operating at the same frequency as the AP. The USB device may modulate a plurality of time-sensitive signals into a current pulse amplitude modulation (PAM) signal, and a plurality of different amplitudes in the current PAM signal is associated with occurrence of high level of a plurality of different combinations of time-sensitive signals in the plurality of time-sensitive signals. That is to say, when high level occurs in different numbers of time-sensitive signals, the modulated current PAM signal will have different power levels. Accordingly, the AP comprises a decoder for demodulating the current PAM signal to obtain a digital signal representing one or more time-sensitive signals transmitted from the USB device to the AP, thereby enabling the transmission of multiple time-sensitive signals from the USB device to the AP.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

Multiple examples are disclosed of SerDes transmitters and receivers. In one example, a transmitter comprises a mapping block to receive a clock signal and a two-bit data signal and to generate a plurality of pairs of digital values; a plurality of current steering blocks, each of the plurality of current steering blocks receiving one of the plurality of pairs of digital values to generate a pair of currents; a current summer and modulation block to receive the pair of currents from each of the plurality of current steering blocks to generate a differential output signal; wherein the differential output signal is a single frequency pulse amplitude modulated signal wherein the single frequency is a frequency of the clock signal.