H03K7/02

HIGH PERFORMANCE PULSE-AMPLITUDE MODULATION (PAM)/NON-RETURN-TO-ZERO (NRZ) TRANSMITTER DRIVER FOR HIGH-SPEED WIRELINE LINKS

Embodiments herein relate to a transmitter which can operate in a non-return-to-zero (NRZ) mode or a pulse amplitude modulation (PAM) mode with three or more levels. The transmitter includes a first driver which processes most significant bits and a second driver which processes least significant bits, in the PAM3 mode. In the NRZ mode, the second driver is turned off but resistances in the second driver are used to optimize impedance in the first driver. Switches can be turned on to couple in resistors in the first driver with resistors in the second driver, for pairs of driver slices. The switches are turned off in the PAM3 mode.

HIGH PERFORMANCE PULSE-AMPLITUDE MODULATION (PAM)/NON-RETURN-TO-ZERO (NRZ) TRANSMITTER DRIVER FOR HIGH-SPEED WIRELINE LINKS

Embodiments herein relate to a transmitter which can operate in a non-return-to-zero (NRZ) mode or a pulse amplitude modulation (PAM) mode with three or more levels. The transmitter includes a first driver which processes most significant bits and a second driver which processes least significant bits, in the PAM3 mode. In the NRZ mode, the second driver is turned off but resistances in the second driver are used to optimize impedance in the first driver. Switches can be turned on to couple in resistors in the first driver with resistors in the second driver, for pairs of driver slices. The switches are turned off in the PAM3 mode.

Photonic transmitter drivers with logic using cascaded differential transistor pairs stepped by supply voltage differences

A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

Photonic transmitter drivers with logic using cascaded differential transistor pairs stepped by supply voltage differences

A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O

Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

Data bus inversion (DBI) on pulse amplitude modulation (PAM) and reducing coupling and power noise on PAM-4 I/O

Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

PHOTONIC TRANSMITTER DRIVERS WITH LOGIC USING CASCADED DIFFERENTIAL TRANSISTOR PAIRS STEPPED BY SUPPLY VOLTAGE DIFFERENCES

A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

PHOTONIC TRANSMITTER DRIVERS WITH LOGIC USING CASCADED DIFFERENTIAL TRANSISTOR PAIRS STEPPED BY SUPPLY VOLTAGE DIFFERENCES

A driver circuit includes digital inputs, such as a first digital input and a second digital input. The digital inputs receive voltages at either a digital high-voltage or a digital low-voltage. The driver circuit has a clock input, an analog output, a first differential pair of transistors connected to the analog output, second differential pairs of transistors connected to the analog output, and voltage limiters connected to the clock input and the second differential pairs of transistors. The voltage limiters supply different voltages to the second differential pairs of transistors, which results in the second differential pairs of transistors providing analog signals to the analog output that are at different voltage steps at, and between, the digital high-voltage and the digital low-voltage.

Sampler reference level, DC offset, and AFE gain adaptation for PAM-N receiver
11018907 · 2021-05-25 · ·

In a PAM-N receiver, sampler reference levels, DC offset and AFE gain may be jointly adapted to achieve optimal or near-optimal boundaries for the symbol decisions of the PAM-N signal. For reference level adaptation, the hamming distances between two consecutive data samples and their in-between edge sample are evaluated. Reference levels for symbol decisions are adjusted accordingly such that on a data transition, an edge sample has on average, equal hamming distance to its adjacent data samples. DC offset may be compensated to ensure detectable data transitions for reference level adaptation. AFE gains may be jointly adapted with sampler reference levels such that the difference between a reference level and a pre-determined target voltage is minimized.

RECEIVER/TRANSMITTER CO-CALIBRATION OF VOLTAGE LEVELS IN PULSE AMPLITUDE MODULATION LINKS
20210144031 · 2021-05-13 ·

A driver circuit of a PAM-N transmitting device transmits a PAM-N signal via a communication channel, wherein N is greater than 2, and the PAM-N signal has N signal levels corresponding to N symbols. A PAM-N receiving device receives the PAM-N signal. The PAM-N receiving device generates distortion information indicative of a level of distortion corresponding to inequalities in voltage differences between the N signal levels. The PAM-N receiving device transmits to the PAM-N transmitting device the distortion information indicative of the level of the distortion. The PAM-N transmitting device receives the distortion information. The PAM-N transmitting device adjusts one or more drive strength parameters of the driver circuit of the PAM-N transmitting device based on the distortion information.