Systems and methods for digital signal processing are provided. A method includes mapping a symbol in a pulse sequence by using a pulse width and a pulse start in the symbol, reading a message using a symbol value for each symbol in a string of symbols, and modifying a drilling configuration according to the message. A device configured to perform the above method is also provided.

Systems and methods for digital signal processing are provided. A method includes mapping a symbol in a pulse sequence by using a pulse width and a pulse start in the symbol, reading a message using a symbol value for each symbol in a string of symbols, and modifying a drilling configuration according to the message. A device configured to perform the above method is also provided.

A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.

A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.

A pulse position modulation circuit includes a delay path that includes a plurality of delay devices coupled in series with each other, a clock being passed through the plurality of delay devices, and a switching circuit that changes a time by which the clock is delayed in each of the plurality of delay devices according to input data.

A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.

A modulator having a pulse density modulator configured to generate from bit stream information a Pulse Density Modulation (PDM) stream based on a PDM clock; and a bit stream adjuster configured to divide the PDM clock into a PDM multi-phase clock, adjust a duration of at least one pulse of the generated PDM stream by selecting a PDM clock phase of the PDM multi-phase clock for sampling the generated PDM stream, and output an adjusted PDM stream.

An array antenna system 3 includes: a transmission unit 14 to which a plurality of pulse signals are given, the pulse signals being obtained by pulse-modulation of digital transmission signals, and including analog transmission signals corresponding to the digital transmission signals, the transmission unit 14 being configured to transmit, as radio signals, the plurality of analog transmission signals included in the plurality of pulse signals; and a plurality of adjustment units 15 configured to perform, for the plurality of pulse signals to be given to the transmission unit 14, an adjustment process for adjusting the relationship of relative phases of the plurality of analog transmission signals included in the plurality of pulse signals.

A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.

A demodulator for pulse-width modulated clock signals is disclosed. In one aspect, the demodulator includes an edge detector configured to detect transitions in a reference clock and output a signal indicative of timing of the detected transitions. The demodulator may also include a modulation detection circuit configured to identify modulation events of at least one pulse-width modulated pulse in the reference clock based on the signal output from the edge detector and output a signal indicative of the at least one pulse-width modulated pulse modulation event being identified. The demodulator may further include a retiming circuit configured to generate an output clock synchronized with the at least one pulse-width modulated pulse modulation event based on the signal output from the modulation detection circuit.