An information processing apparatus which is capable of maintaining the amount of radiation noise from a semiconductor integrated circuit constant. A voltage value information storage unit holds information indicative of a voltage to be applied to the semiconductor integrated circuit. A sub CPU modulates a clock frequency of a clock to be supplied to the semiconductor integrated circuit with a modulation width determined based on the information held in the voltage value information storage unit and supplies the clock.

An information processing apparatus which is capable of maintaining the amount of radiation noise from a semiconductor integrated circuit constant. A voltage value information storage unit holds information indicative of a voltage to be applied to the semiconductor integrated circuit. A sub CPU modulates a clock frequency of a clock to be supplied to the semiconductor integrated circuit with a modulation width determined based on the information held in the voltage value information storage unit and supplies the clock.

Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

The present disclosure relates to a frequency modulation device, a switching power supply and a frequency modulation method thereof. The device includes: a waveform generation unit (10) configured to generate a periodic signal required for performing frequency modulation on a clock signal of a switching power supply to be controlled; a frequency modulation unit (20) configured to perform voltage-current conversion and arithmetic processing based on the periodic signal to obtain a frequency modulation current required for performing the frequency modulation on the clock signal of the switching power supply to be controlled; and an RC oscillation unit (30) configured to perform RC oscillation processing based on the frequency modulation current to obtain a frequency oscillation signal as the clock signal of the switching power supply to be controlled.

In an analog-to-frequency converting circuit, a set of switches receive a first sense signal indicative of a current and provides a second sense signal that alternates between an original version of the first sense signal and a reversed version of the first sense signal, under control of a switching signal. An integral comparing circuit integrates the second sense signal to generate an integral value and generates a train of trigger signals. Each trigger signal is generated when the integral value reaches a preset reference. A compensation circuit compensates for the integral value with a predetermined value in response to each trigger signal. A control circuit generates the switching signal such that a time interval during which the second sense signal is the original version and a time interval during which the second sense signal is the reversed version are substantially the same.

In an analog-to-frequency converting circuit, a set of switches receive a first sense signal indicative of a current and provides a second sense signal that alternates between an original version of the first sense signal and a reversed version of the first sense signal, under control of a switching signal. An integral comparing circuit integrates the second sense signal to generate an integral value and generates a train of trigger signals. Each trigger signal is generated when the integral value reaches a preset reference. A compensation circuit compensates for the integral value with a predetermined value in response to each trigger signal. A control circuit generates the switching signal such that a time interval during which the second sense signal is the original version and a time interval during which the second sense signal is the reversed version are substantially the same.

An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.

An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.

A wireless data transmitter including: a data modulator adapted to modulate a data signal based on a frequency signal; and at least one antenna adapted to wirelessly transmit the modulated data signal and the frequency signal independently.