An embodiment in accordance with the present invention provides a system and method of physically modulating a digital signal across a medium. A signal is sent one bit at a time (serially) as a period of high voltage followed by a period of low voltage. The present invention includes several major advantages. One advantage is that the code to execute the method is very lightweight. Another advantage is that the signals require no synchronization source. The signals of the present invention function as their own synchronization.

A PFM control circuit includes a switching circuit, a slope-decision circuit, a flip-flop, a first and a second comparison circuits. The first comparison circuit outputs a first signal according to an output voltage of a power conversion circuit. The switching circuit outputs a switching signal according to an output current of the power conversion circuit. The slope-decision circuit outputs a slope modulation voltage, and determines a slope modulation voltage with a first or a second slope according to the switching signal. The second comparison circuit outputs the second signal according to the slope modulation voltage. The flip-flop outputs a control signal to the power conversion circuit according to the first and the second signals. When the slope modulation voltage has the first or the second slope, the control signal has a first or a second frequency accordingly. The first frequency is higher than the second frequency.

A frequency regulator and a frequency regulating method thereof, and an electronic device are disclosed. The frequency regulator includes: a signal processing circuit configured to generate a frequency control word according to a frequency regulating coefficient and an input frequency; and a frequency regulating circuit configured to receive the frequency control word and to generate and output an output signal having a target frequency according to the frequency control word. The frequency regulating coefficient is an arbitrary positive real number and is expressed as M.m, M is an integer portion of the frequency regulating coefficient and is a natural number, and m is a decimal portion of the frequency regulating coefficient.

A frequency regulator and a frequency regulating method thereof, and an electronic device are disclosed. The frequency regulator includes: a signal processing circuit configured to generate a frequency control word according to a frequency regulating coefficient and an input frequency; and a frequency regulating circuit configured to receive the frequency control word and to generate and output an output signal having a target frequency according to the frequency control word. The frequency regulating coefficient is an arbitrary positive real number and is expressed as M.m, M is an integer portion of the frequency regulating coefficient and is a natural number, and m is a decimal portion of the frequency regulating coefficient.

Methods, apparatus, systems and articles of manufacture are disclosed to adjust an operating mode of a power converter. An example apparatus includes a first transistor having a gate terminal, a first current terminal, and a second current terminal, the first current terminal to be coupled to a second transistor and an inductor of a power converter, a capacitor coupled to the second current terminal, a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the logic gate output coupled to the gate terminal, a comparator having a comparator input and a comparator output, the comparator input coupled to the capacitor and the second current terminal, a multiplexer coupled to the comparator output, a first flip-flop coupled to the multiplexer and the second logic gate input, and a second flip-flop coupled to the multiplexer and the first flip-flop.

Methods, apparatus, systems and articles of manufacture are disclosed to adjust an operating mode of a power converter. An example apparatus includes a first transistor having a gate terminal, a first current terminal, and a second current terminal, the first current terminal to be coupled to a second transistor and an inductor of a power converter, a capacitor coupled to the second current terminal, a logic gate having a first logic gate input, a second logic gate input, and a logic gate output, the logic gate output coupled to the gate terminal, a comparator having a comparator input and a comparator output, the comparator input coupled to the capacitor and the second current terminal, a multiplexer coupled to the comparator output, a first flip-flop coupled to the multiplexer and the second logic gate input, and a second flip-flop coupled to the multiplexer and the first flip-flop.

A power supply device includes a pulse frequency modulation controller circuitry and a cycle controller circuitry. The pulse frequency modulation controller circuitry is configured to adjust a transiting speed of a first signal according to at least one control bit, and to compare the first signal with a first reference voltage to generate a second signal, and to generate a driving signal to a power converter circuit according to an output voltage, a second reference voltage, and the second signal, in which the power converter circuit is configured to generate the output voltage according to the driving signal. The cycle controller circuitry is configured to detect a frequency of the driving signal according to a clock signal having a predetermined frequency, in which the predetermined frequency is set based on a frequency range capable of being heard by humans

Described are systems and methods for identifying the phase and polarization of independent modulation streams in quadrature channels of a coherent transmission system by using digital code. As a result, phase rotation and polarization of streams that during transmission may have become rotated and swapped around in the channel are correctly labeled and depermuted according to a known and predictable order.

A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.

A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.