The present disclosure relates to a method of analyzing a pulse modulated signal, wherein the method comprises: receiving a pulse modulated signal; determining a dynamic threshold level based on a period of the pulse modulated signal and the pulse modulated signal; and demodulating the pulse modulated signal by the dynamic threshold level. Moreover, a signal analysis instrument for analyzing a pulse modulated signal is described.

The present disclosure relates to a method of analyzing a pulse modulated signal, wherein the method comprises: receiving a pulse modulated signal; determining a dynamic threshold level based on a period of the pulse modulated signal and the pulse modulated signal; and demodulating the pulse modulated signal by the dynamic threshold level. Moreover, a signal analysis instrument for analyzing a pulse modulated signal is described.

A frequency regulator and a frequency regulating method thereof, and an electronic device are disclosed. The frequency regulator includes: a signal processing circuit configured to generate a frequency control word according to a frequency regulating coefficient and an input frequency; and a frequency regulating circuit configured to receive the frequency control word and to generate and output an output signal having a target frequency according to the frequency control word. The frequency regulating coefficient is an arbitrary positive real number and is expressed as M.m, M is an integer portion of the frequency regulating coefficient and is a natural number, and m is a decimal portion of the frequency regulating coefficient.

An automatic frequency modulation circuit and an automatic frequency modulation method using efficiency statistics as a reference for frequency modulation applied to a pulse-width modulation (PWM) system are disclosed. The automatic frequency modulation circuit includes an oscillator unit, an on-time generating unit, a frequency adjusting unit and a frequency selecting unit. The oscillator unit receives a reference current and generate a clock signal. The on-time generating unit, coupled to the oscillator unit, receives a reference voltage and a first voltage of the oscillator unit and generates an on-time signal. The frequency adjusting unit, coupled to the on-time generating unit, receives the on-time signal and a PWM signal and generates a frequency adjusting signal. The frequency selecting unit is coupled to the frequency adjusting unit and automatically adjusts an original frequency according to the frequency adjusting signal to generate an adjusted frequency.

An automatic frequency modulation circuit and an automatic frequency modulation method using efficiency statistics as a reference for frequency modulation applied to a pulse-width modulation (PWM) system are disclosed. The automatic frequency modulation circuit includes an oscillator unit, an on-time generating unit, a frequency adjusting unit and a frequency selecting unit. The oscillator unit receives a reference current and generate a clock signal. The on-time generating unit, coupled to the oscillator unit, receives a reference voltage and a first voltage of the oscillator unit and generates an on-time signal. The frequency adjusting unit, coupled to the on-time generating unit, receives the on-time signal and a PWM signal and generates a frequency adjusting signal. The frequency selecting unit is coupled to the frequency adjusting unit and automatically adjusts an original frequency according to the frequency adjusting signal to generate an adjusted frequency.

Systems, apparatuses, and methods for implementing a hybrid asynchronous gray counter with a non-gray zone detector are described. A circuit includes an asynchronous gray counter coupled to control logic. The control logic programs the asynchronous gray counter to operate in different modes to perform various functions associated with a high-performance phase-locked loop (PLL). In a first mode, the asynchronous gray counter serves as a frequency detector to count oscillator cycles within a reference clock cycle. In a second mode, the asynchronous gray counter serves as a coarse phase detector to detect a phase error between a feedback clock and a reference clock. In a third mode, the asynchronous gray counter serves as a multi-modulus divider to divide an oscillator clock down to create a feedback clock. Using a single asynchronous gray counter for three separate functions reduces power consumption and area utilization.

Disclosed is a method for spreading spectrum, which includes: acquiring a modulation signal corresponding to a clock signal, when the clock signal is detected; and spectrum spreading the clock signal according to the modulation signal, wherein the modulation signals respectively corresponding to two adjacent clock signals are opposite in phase. The present disclosure further provides a chip, a display panel, and a computer readable storage medium. The present disclosure solves the technical problem of poor spread spectrum effect on dual clock signals.

A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator configured to generate an output clock, and a sub-sampling PLL circuit configured to receive, from the voltage-controlled oscillator, the generated output clock as feedback, and perform a phase-locking operation on the received output clock. The sub-sampling PLL circuit includes a buffer configured to buffer the received output clock, and the sub-sampling PLL circuit is further configured to adaptively adjust an internal signal to maintain a loop bandwidth of the sub-sampling PLL circuit, based on a change of a characteristic of the buffer according to at least one of process, voltage, and temperature (PVT) change.

An automatic frequency modulation circuit and an automatic frequency modulation method using efficiency statistics as a reference for frequency modulation applied to a pulse-width modulation (PWM) system are disclosed. The automatic frequency modulation circuit includes an oscillator unit, an on-time generating unit, a frequency adjusting unit and a frequency selecting unit. The oscillator unit receives a reference current and generate a clock signal. The on-time generating unit, coupled to the oscillator unit, receives a reference voltage and a first voltage of the oscillator unit and generates an on-time signal. The frequency adjusting unit, coupled to the on-time generating unit, receives the on-time signal and a PWM signal and generates a frequency adjusting signal. The frequency selecting unit is coupled to the frequency adjusting unit and automatically adjusts an original frequency according to the frequency adjusting signal to generate an adjusted frequency.

Methods, systems, and apparatus to increase common-mode transient immunity in isolation devices is disclosed. An example apparatus includes a current mirror including an input terminal and an output terminal; a transistor including a gate terminal, a first current terminal, and a second current terminal, the gate terminal coupled to a reference voltage terminal, the first current terminal coupled to the input terminal of the current mirror, and the second current terminal coupled to an input node; a buffer including an input terminal and an output terminal, the input terminal of the buffer coupled to the output terminal of the current mirror; and a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the output terminal of the buffer.