An optical receiver device includes a boost converter circuit, an optical receiver circuit, and a pulse width modulation controller circuitry. The boost converter circuit is configured to convert a supply voltage according to a pulse width modulation signal, in order to generate an output voltage. The optical receiver circuit is configured to set a gain according to the output voltage, in order to convert an optical signal to a data signal according to the gain. The pulse width modulation controller circuitry is configured to perform a digital to analog conversion according to a control code to gradually adjust a current associated with the output voltage, and to compare the output voltage with a reference voltage to generate the pulse width modulation signal.

A power monitor includes a detecting circuit, a processing circuit, and a warning circuit. The detecting circuit detects a first abnormal condition of a primary side circuit and a second abnormal condition of a secondary side circuit. The processing circuit calculates a first class and a first occurring number of the first abnormal condition, and calculates a second class and a second occurring number of the second abnormal condition. The processing circuit determines whether the first occurring number is larger than a first predetermined number corresponding to the first class; if it is, the processing circuit outputs a first abnormal signal. The processing circuit determines whether the second occurring number is larger than a second predetermined number corresponding to the second class; if it is, the processing circuit outputs a second abnormal signal. The warning circuit outputs a warning signal according to the first or the second abnormal signal.

An improved power converter produces power through a power switch in response to an activation signal that has an on-time and a switching frequency. An on-time signal has a constant on-time and controls the on-time of the activation signal. An error signal indicates that the switching frequency is not equal to a reference frequency. A step up signal and a step down signal are based on the error signal. A count signal is increased in response to the step up signal and decreased in response to the step down signal. An on-time pulse has a duration that is related to a value of the count signal. The on-time pulse controls the constant on-time of the on-time signal and maintains the switching frequency at about the reference frequency.

An improved power converter produces power through a power switch in response to an activation signal that has an on-time and a switching frequency. An on-time signal has a constant on-time and controls the on-time of the activation signal. An error signal indicates that the switching frequency is not equal to a reference frequency. A step up signal and a step down signal are based on the error signal. A count signal is increased in response to the step up signal and decreased in response to the step down signal. An on-time pulse has a duration that is related to a value of the count signal. The on-time pulse controls the constant on-time of the on-time signal and maintains the switching frequency at about the reference frequency.

A class D amplifier circuit receives an analog audio signal with a first reference voltage as its center level, and outputs an output pulse signal having a duty cycle that corresponds to the analog audio signal. A bias circuit generates a second reference voltage having a voltage level obtained as a division of the first reference voltage and the power supply voltage. A periodic voltage generating circuit of the class D amplifier circuit generates a periodic voltage having a triangle waveform or otherwise a sawtooth waveform having an amplitude that corresponds to the second reference voltage.

In an embodiment an isolated gate driver device includes a low-voltage section having a control input configured to receive a PWM control signal with a switching frequency from a control stage, a high-voltage section, galvanically isolated from the low-voltage section the high-voltage section including a driving output configured to provide a gate-driving signal as a function of the PWM control signal to a power stage having at least one switch, a feedback input configured to receive at least one feedback signal indicative of an operation of the power stag, and an ADC module configured to convert the feedback signal into a digital data stream and a conversion-control module coupled to the ADC module and configured to provide a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal.

In an embodiment an isolated gate driver device includes a low-voltage section having a control input configured to receive a PWM control signal with a switching frequency from a control stage, a high-voltage section, galvanically isolated from the low-voltage section the high-voltage section including a driving output configured to provide a gate-driving signal as a function of the PWM control signal to a power stage having at least one switch, a feedback input configured to receive at least one feedback signal indicative of an operation of the power stag, and an ADC module configured to convert the feedback signal into a digital data stream and a conversion-control module coupled to the ADC module and configured to provide a conversion-trigger signal designed to determine a start of a conversion for acquiring a new sample of the feedback signal.

An integrated circuit includes a pulse width modulator. The pulse width modulator includes a multiplexer that receives a plurality of data delay signals. Each of the data delay signals is based on a data signal and a respective clock phase signal. The multiplexer includes a first multiplexer stage and a second multiplexer stage. The first multiplexer stage receives all of the data delay signals and has a relatively large delay. The second multiplexer stage receives to output signals from the first multiplexer stage and has a relatively small delay. The second multiplexer stage outputs a pulse width modulation signal that can have a pulse width corresponding to the offset between two adjacent clock phase signals.

Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.