The present disclosure describes embodiments of driver circuit. The driver circuit includes a first impedance element electrically coupled to a first inverter circuit and a second impedance element electrically coupled to the first impedance element and a second inverter circuit. For a first encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a first current flows through the first and second impedance elements, the first current having a first value and a first direction. For a second encoding using the driver circuit, the first inverter circuit and the second inverter circuit are controlled such that a second current flows through the first and second impedance elements, the second current having a second value and a second direction. The first value is substantially the same as the second value and the first direction is opposite to the second direction.

A 4-level pulse amplitude modulation (PAM-4) decoder including: a comparator configured to receive first input data, second input data, and a clock signal and output first comparison data and second comparison data, wherein the first comparison data and the second comparison data are comparison results for the first input data and the second input data; a clock delay circuit configured to delay the clock signal and generate a delayed clock signal; and a time-windowed least significant bit (LSB) decoder configured to receive the first comparison data, the second comparison data, and the delayed clock signal, wherein the time-windowed LSB decoder is configured to perform a decoding when the delayed clock signal is at a first level.

An isolator according to one embodiment includes: a modulation analog-to-digital converter converts the input analog signal into a digital data signal of a pulse train corresponding to the amplitude of the input analog signal, and outputs the digital data signal; an attribute signal detection circuit detects an attribute of the input analog signal and outputs input attribute information related to the attribute of the input analog signal; a high speed feedback encoder encodes the digital data signal based on the input attribute information and outputs a first encoded signal; an edge encoder outputs a second encoded signal; an insulated transmission circuit outputs a transmission signal transmitted through the insulation unit in response to the second encoded signal; and a demodulation circuit outputs a demodulated digital data signal obtained by demodulating the second encoded signal and/or the input attribute information, based on the transmission signal.

An isolator according to one embodiment includes: a modulation analog-to-digital converter converts the input analog signal into a digital data signal of a pulse train corresponding to the amplitude of the input analog signal, and outputs the digital data signal; an attribute signal detection circuit detects an attribute of the input analog signal and outputs input attribute information related to the attribute of the input analog signal; a high speed feedback encoder encodes the digital data signal based on the input attribute information and outputs a first encoded signal; an edge encoder outputs a second encoded signal; an insulated transmission circuit outputs a transmission signal transmitted through the insulation unit in response to the second encoded signal; and a demodulation circuit outputs a demodulated digital data signal obtained by demodulating the second encoded signal and/or the input attribute information, based on the transmission signal.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.

A memory controller in an integrated circuit system includes a transmitter module. The transmitter module receives from a processor a bit stream including a given symbol to be transmitted according to pulse-amplitude-modulation (PAM) with N signal levels on a first lane of multiple lanes. The lanes connect the transmitter module to a memory module in the integrated circuit system. The transmitter module identifies parameters for cancelling crosstalk from other lanes on the first lane. The parameters are identified based on a pending transition in signal levels in each of the other lanes. The transmitter module superposes the parameters of the other lanes on the given symbol to adjust the given symbol on the first lane. A digital-to-analog converter (DAC) on the first lane generates an analog output to the memory module. The analog output represents the adjusted given symbol.